CGTalk - SGI launches new MIPS® R16000 processor

DotPainter

12-28-2002, 09:50 AM

The main difference, other than 64 bit words, between MIPS and Intel chips is the fact that the MIPS is a RISC (Reduced Instruction Set) Processor. This means that there are fewer low level CPU instructions, thereby allowing high level program operations to be executed with fewer CPU cycles. Intels chips, on the other hand, have a verrry long instruction pipeline, or in other words it takes longer for the CPU to actually perform a given instruction. Yes, Intel chips have the horsepower, but they are known for being very inefficient. This is also the same reason why a Athlon chip, which has a shorter instruction pipeline, can outperform an intel chip that is 3-400 MHz faster. However, AMD chips are still less efficient than RISC chips and therefore slower.

In addition to this, L2 Cache is faster than L1 cache which is in turn faster than RAM, which means that there is more data available for the CPU to actually process without having to wait for relatively long fetches for data from RAM or even (gasp!) the hard disk.

beaker

12-28-2002, 11:44 AM

When the Alpha was still around, the 667mhz at the time performed about 2x the speed of a 1.2 ghz P3.
Blue Sky rendered Ice Age on a farm of 500 & 667 mhz alpha boxes.

So mhz doesn't mean everything. This is why AMD call their processor XP2200 when it is actually a 1.8ghz. It is to fight the whole marketing machine of intel that puts into the consumer mind that the higher the number the faster it is.

eliseu gouveia

12-28-2002, 01:55 PM

Originally posted by Dj_Grfx
People like you are the reason intel is the marketing monster it is, throw em some guys in blue paint spouting off numbers like 500 googlehertz, throw it in a box called dell and the masses will eat it up like candy....oh yeah i forgot make sure also to say it makes the internet faster

I-it doesnt? A-are you sure? OMG!!... :)

Hey, I only have a Celeron 700Mhz because I wanted a thing that could run Photoshop5.5 in it for my work and that´s what they had at that time on the shelves.

But you are right, perhaps everybody should start wearing swastics and shooting "people like me" who dares not to know all the inside-out buz of the High-tech biz.

MacRonin

12-28-2002, 03:40 PM

Here here!

Shoot the PC wankers!

;^p

http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/A1387A29AC1C2AE087256C5200611780/$file/PPC970_MPF2002.pdf

Mmmm...

eskil

12-28-2002, 04:08 PM

Eskils 101 in why cpus are fast or slow:

there are a number of reasons why a cpu is either fast or slow and Mhz is just one.

The main one is memory management. (there are many others where intel sucks but for now lets stay with memory management)

Deep in side the processor there is something called registers, they are the "shot term memory" used to do calculations. and instruction can be: "multiply register 1 with register 3 and put the output in register 4" a 32-bit machine can store 32 bits in one register while a 64-bit processor can store 64 bits per register. so a 64 bit processor doesn't get faster just because its 64 bits, unless you need to work with 64bit data (memory allocations larger then 4gigs, double precision floating point values generally things that SGI and other workstation/server/supercomuter computers manufacturer needs) in a 32-bit architecture a processor needs to split the 64 bit data in to two and that's why they are slow on 64 bit computations.

If you need to read data outside that's when it gets slow. how often you need to do this depends on the number registers. a modern CPU (like the one in a PS2) has +512 registers. a pentium 4 has 8 (yeah, yeah, I know they have their tricks... dont flame me).

Ok so how slow is the memory to read? well it takes about 30+ cycles on a Athlon to read 32 bits of data form the main memory, compare this to the awesome computing power of the Athlon, 3 floating point operations per cycle!

so what do we do? well we create cashes. cashes is a small copy of a part the main memory put the cpu for easy access. the level one cache has an access time of 11 cycles! still you can do 33 multiplication's in that time...

Now you can start to see why only 8 registers might not be so good.

So why don't make huge cache? well for a few reasons, first they are expensive (and so is the R16000). but the biggest problem is that if they are large they will become slower to access because of extended time needed to find stuff in them. That is why one has multiple cashes. some small and fast, and some large and a bit slower (like the L2 on the R16000)

In a modern Intel/AMD CPU there are lots of things like pre fetching, long pipes, long branch prediction, and other things to combat this bad basic design. they all have their own side effects, and they cost money and take up space and power consumption.

Mots other CPUs like the Risc, PowerPC, Alpha or I64 have much cleaner design.

E

meloncully

12-28-2002, 05:23 PM

Thanks E!!

:buttrock: :buttrock: :applause: :love: :thumbsup: :bowdown: :bowdown:

Per-Anders

12-28-2002, 07:33 PM

Thanks guys. I knew not to go on the mhz rating, but i just didn't know enough about CPU's or specifically what made this chip good compared to the any other processor.

eliseu gouveia

12-28-2002, 09:01 PM

I thank you too, that was very educational. :)

DotPainter

12-29-2002, 02:06 AM

Nice lesson E!

One addition, if you will:
MHz for a cpu only tells you how many cycles there are per second. A cycle is basically a state transition from a high voltage to a lower voltage and is carried as a electrical pulse throughout all of the devices connected to the main system bus. If one was to visualize a sequence of these state transitions, it would look like a square sine wave. The more of these transitions occur in a second, the faster the clock rating of the CPU. A clock is the most fundamental component of integrated circuit logic and controls the flow of current through the chip and connected data buses by generating the clock signal which is the what the cpu cycle is. It is a synchronization mechanism that allows all of the data transfers between CPU registers, memory bus and data registers. Most often the circuitry is set up so that devices operate either on the rising edge of the clock signal, the falling edge of the clock signal or both. DDR memory is based upon the use of both the rising and falling edge of the clock cycle to transfer data to the cpu registers, thereby doubling the data transfer rate. Quad pumped DDR refers to the fact that there 4 data channels each operating on the rising and falling edge of the clock signal, effectively quadrupling the max theoretical amount of data transferred.

However, this is a very simplified view of the system. In actual fact there are mutliple clocks. One for the CPU and one for the Memory Bus. The CPU clock is always faster than the clock for the memory bus. This is why there are so many schemes to like DDR for doubling or quadrupling the maximum theoretical memory bandwith. The CPU clock controls transfers between cache memory, data registers, the arithmetic processing unit (the part of the cpu which actually performs mathematical operations) and other blocks within the cpu. The term pipeline generally refers to how many cycles it takes to accomplish all of the data transfers and other operations necessary to actually move data to and from all of the special purpose circuits on the chip necessary to perform a operation and is highly dependant on the architecture of the chip itself. The more modules and transfers, the more cycles to execute an operation.

So as we can see, there are many, many things that impact on actual CPU performance other than MHz.

Understanding microprocessors (http://arstechnica.com/paedia/c/cpu/part-1/cpu1-1.html)

Look for the link to a description of the P4 pipeline and you see how inefficient it is.

Memory bandwith and latency (http://www.arstechnica.com/paedia/b/bandwidth-latency/bandwidth-latency-1.html)

Obviously, even though the SGI machine is powerful, only companies with deep pockets can afford it. Compared to the general purpose computing market catered to by Intel and AMD, this is a niche market to say the least. And with Intel and AMD offering faster and faster CPUs every year, the need for such boxes is steadily being eroded.

urgaffel

12-29-2002, 03:16 AM

Speaking of processors, what's inside one of them fancy Inferno stations? :)

Eskil: Ok so how slow is the memory to read? well it takes about 30+ cycles on a Athlon to read 32 bits of data form the main memory, compare this to the awesome computing power of the Athlon, 3 floating point operations per cycle!

so what do we do? well we create cashes. cashes is a small copy of a part the main memory put the cpu for easy access. the level one cache has an access time of 11 cycles! still you can do 33 multiplication's in that time...

Now you can start to see why only 8 registers might not be so good.

...

What? I'm lost :/

beaker

12-29-2002, 07:18 AM

>>Speaking of processors, what's inside one of them fancy Inferno stations?

Inferno is in a deskside onyx. So depending on how old it is, it could be as slow as a r10k 195, all the way up to a r14k 600 (probably a r16k 700 once the onyx starts supporting it). It really isnt the processor that makes the inferno so great, but the bandwidth of it and the amazing SD/HD I/O board that the onyx has.

eskil

12-29-2002, 09:12 AM

thanks every one.

I would like to point out:

Im not saying that a R160000 is faster then a Pentium 4. My guess is that if given the chance both SGI and Intel will be able to show test scores where they outperforms the competition. (The R160000 will almost certainly outperform the P4 with 64 bit instructions). It depends on the code you are testing. you can write code that will run optimal for one processor and will run poorly on an other.

You must remember that even though Intel and AMD has the limitation of only 8 registers, they have huge amounts of money to spend on making it fast anyway.

The P4 is also poorly designed, it was cut down for budget, and the marketing department demanded high Mhz rather then a fast processor. that is why a 1Ghz P3 out performed a 1.4Ghz P4.

So why does intel only have 8 registers? Its like tying to build a F1 car out of an old beetle, so why not just start over?

Because every win app in the world is written for the same instructions set, an instruction set that dates back to the 8086 (that's before the 286). back then every one wrote completely new instruction sets for each new processor and no one had any idea that the decisions made back then would still matter so may years later. So we are still writing code for a very old processor.

What you can do is to add extra instructions, that do new cool things, (like MMX, SSI and the velocity engine) but then you have to write special code for it, and special code if it does not exist too something that makes programming less easy/fun.

Now a days when designing a brand new processor one anticipates it to live a lot longer then one generation and therefor one can design them better, many ideas that seem to be revolutionizing in one generation of cpu turns out not to be that fast later on (like big/little engine). I remember a few years back when the concept of RISC came out and most people calmed that RISCs would outperform SISCs (non RISCs) so much that in the future every thing had to be RISCs in order to keep up, that didn't turn out to be true.

Well, intel have tried start from scratch a few times. with the Power PC, and now the I64 Itanium. But they have never been able to produce a so much faster CPU that people will go threw the hassle of recompiling the software. The design of the Itainium is kind of funny because it is not at all forward looking. (you would think that they would learn....)

The basic idea with the Itanium is that the compiler knows exactly what the cpu can do and how fast it is and can therefor compile code that is faster because it is more optimal for the hardware.

Let me give you an example: if we would have the instruction "multiply register 3 and 5 and put the output in register 6" in an ordinary CPU, The Itanium code would also include information like what math unit should be used. in that way the cpu doesn't have to figure that out on the fly, its already in the code! This is obviously faster, but if you in the next generation add an other math unit it will never be used, or you have to re compile your code whit a copiler that knows about the new CPU features, or you have to design a very complex system to try to override the instructions on where to execute the math instruction, and the hole point of the design is gone.

E

ilasolomon

12-29-2002, 01:52 PM

all the cgtalkers use iNTEL, AMD or PowerPC (or Motorola), maybe one or 2 use Alpha but I couldn't say someone has a SGI workstation with MIPS (Risk) cpu around! so take it easy...just
read the article & wish the next AMD could beat it! :) ;) :D
God bless AMD!
Regards
Ila

Thalaxis

12-30-2002, 05:24 PM

Wow, I don't even know where to start with this... it's so full of errors as to be almost funny.

The fact that the P4 has a 20-stage pipeline doesn't mean much when it's running at over 3x the clock speed AND has more execution resources than this new MIPS beastie.

You obviously don't understand what RISC and CISC mean, or how processors decode instructions.

You also clearly don't understand caching.

The Athlon's shorter pipeline isn't the reason it performs as well as a higher-clocked P4, but then it was designed differently; Intel can drive far higher clock speeds than everyone else on the planet, because they're better at semiconductor fabrication than everyone else on the planet. Hence, they are taking full advantage of that with the P4, because they believe that the return on investment is better than would be possible by increasing parallelism. AMD took a more middle of the road approach; they have a fairly long pipeline in order to allow for higher clock speeds, but their compromise is that the Athlon has more parallel execution resources than the P4.

Originally posted by DotPainter
The main difference, other than 64 bit words, between MIPS and Intel chips is the fact that the MIPS is a RISC (Reduced Instruction Set) Processor. This means that there are fewer low level CPU instructions, thereby allowing high level program operations to be executed with fewer CPU cycles. Intels chips, on the other hand, have a verrry long instruction pipeline, or in other words it takes longer for the CPU to actually perform a given instruction. Yes, Intel chips have the horsepower, but they are known for being very inefficient. This is also the same reason why a Athlon chip, which has a shorter instruction pipeline, can outperform an intel chip that is 3-400 MHz faster. However, AMD chips are still less efficient than RISC chips and therefore slower.

In addition to this, L2 Cache is faster than L1 cache which is in turn faster than RAM, which means that there is more data available for the CPU to actually process without having to wait for relatively long fetches for data from RAM or even (gasp!) the hard disk.

Thalaxis

12-30-2002, 05:27 PM

Originally posted by eskil
computers manufacturer needs) in a 32-bit architecture a processor needs to split the 64 bit data in to two and that's why they are slow on 64 bit computations.

Amusing statement in light of the fact that most modern renderers rely heavily on 64-bit arithmetic, and the P4 is giving even the Power4 with its massive 100 GB/s system bus a run for its money there....

Oh, and by the way -- the x87 FPU supports 80-bit floating point ops. I don't think that they would have to split 64-bit ones into 32-bit ones just to crunch them.

The number of registers and the addressable memory with 32-bit addressing are definitely limitations, though... and those are some of the things that drove certain design decisions in the Hammer and Itanium families.

Thalaxis

12-30-2002, 05:36 PM

Originally posted by eskil
Im not saying that a R160000 is faster then a Pentium 4. My guess is that if given the chance both SGI and Intel will be able to show test scores where they outperforms the competition. (The R160000 will almost certainly outperform the P4 with 64 bit instructions). It depends on the code you are testing. you can write code that will run optimal for one processor and will run poorly on an other.

The odds that the R16k will ever be able to keep up with the P4 when the 4 GB limit isn't an issue aren't very good. It's a 4-issue superscalar CPU... the P4 is a 6-issue. So in addition to having comparable system bus throughput and a big clock speed advantage, it has a version of simultaneous multithreading and more execution resources to work with.

The P4 is also poorly designed, it was cut down for budget, and the marketing department demanded high Mhz rather then a fast processor. that is why a 1Ghz P3 out performed a 1.4Ghz P4.

That's a massive (though unfortunately common) misconception. If it were such a poor design, why is it almost neck and neck with Power4, and ahead of almost everything else? It's biggest weakness is that it doesn't get along with legacy code.

The reason that it doesn't do so well compared to most other processors at the same speed is that speed is nothing more than a design parameter, not a particularly useful performance metric in modern times when processor architectures are becoming so different from each other.

Well, intel have tried start from scratch a few times. with the Power PC, and now the I64 Itanium. But they have never been able to produce a so much faster CPU that people will go threw the hassle of recompiling the software. The design of the Itainium is kind of funny because it is not at all forward looking. (you would think that they would learn....)

PowerPC? Intel was never involved in that.
Maybe you should look at the performance data again. Itanium2 is faster than many people think it should be, all things considered.

Of course, given the level of effort that went into it (between HP and Intel I think the current tally is around $7 BILLION), it SHOULD be pretty impressive.

DotPainter

12-30-2002, 09:19 PM

Thalaxis:

You are right, I made errors. Namely, one being that L2 cache is faster than L1 when the opposite is true. Also, you are right that the powerPC was not developed by intel.

However, the ultimate point that we all agree on is that MHz is not the determining factor in performance. I haven't seen any comparisons between P4s and SGI boxes, mainly because of the fact that they are two different architectures (unix/windows, risc/cisc, x86/mips). Hopefully they will post some or someone knows of some, it would be interesting to see the results. But still it is like comparing apples to oranges. The MIPS@R16000 is only running at 700 MHz. So to be fair you would have to compare it to a PIII 700 MHz, then you would see how much the MIPS outperforms the Pentium clock for clock, which is ultimately what I was getting at. The architecture and pipeline of the MIPS is hightlly optimized for more performance at lower clock speeds which is similar to AMDs approach. An AMD 2700+ can compete with the pentium 2.8 GHz in many tests, but in all actuallity it is only running at around 2.1 GHz! Keep that in mind when you are looking at the comparisons.

The fact that Intel has a high MHz rating does not make it better at actually performing individual calculations, it just has a faster clock, which does ultimately help it perform despite itself. The architecture of the Pentium is such that it needs higher MHz in order to give good performance, while other chips can perform the same with lesser MHz. I am not saying that it isn't good that they can fabricate such fast chips, rather I am saying that everything people say about them is not pure misconception either. Therefore, I guess it is like saying two cars have equal horsepower, but one gets better oomph or goes from 0-60 faster than the other. Therefore you could extrapolate that the engine in the car that wins the race is put together better and has a more efficient pipeline...... The only thing now is who can match the raw horsepower of the P4!

;)

Anyway, thanks for the correction....

Thalaxis

12-30-2002, 10:10 PM

DotPainter:

I can't find SPEC submissions for the Fuel, but here are some for their Origin using one of the choices in processors for the Fuel:

SGI SGI Origin 300 1X 600MHz R14000A 495 472

For comparison, here is the P4 at 3.06 GHz:
Dell Precision WorkStation 340 (3.06 GHz P4) 982 972

(The last two numbers are the peak and base results.)

The thing is... the R16k has (I was mistaken when I wrote about it earlier) LESS bandwidth (3.2 GB/s) than a current P4 (4.2 GB/s), less than 1/3 the clock speed, AND no better peak instructions per clock cycle... so the statement that it's more optimzed for performance at lower clock speeds doesn't make any sense.

If you compare processors at a given technology node (e.g. .13 micron, SoI, etc) you find that the P4 does remarkably well -- if you use current compilers.

To make your analogy more appropriate, it's like comparing engine RPM's and saying that the one with lower RPM's is less powerful.

Saab's V6 engine runs at around 1/3 the RPM's of my Alero's V6, yet if I remember correctly (I might have this backward, but the point is still valid) comparable torque and higher horsepower. I think it also has less displacement, but the end result is that it performs better than mine.

If you want to compare the P4's capabilities to that of the R16k, the more appropriate analogy would be that it has higher RPM's, more torque, more displacement, and higher horsepower to go with it... and one major tradeoff is that it also has much higher fuel consumption (check the power dissipation sometime, the 3.06 GHz P4 with HT enabled and running full-throttle with 2+ threads has a maximum power dissipation of 100 watts; I suspect that the R16k is down in the 30-50 range, but I'm not sure exactly).

eskil

12-30-2002, 11:05 PM

You people just don't seem to get it, I never said the Itanium was slow, I never claimed P4 to be slow either, nor the R16000 to be fast I just gave a few answers to what makes some CPUs faster then others, and what makes up for the many design issues that the CPU designers are faced with.

Did you just have to make this in to religious flame war on what CPU is the best one?

E

Thalaxis

12-30-2002, 11:10 PM

No, I just had to correct your poorly explained and not entirely accurate or complete explanations.

Christian Mir

12-30-2002, 11:49 PM

Originally posted by Thalaxis
DotPainter:

I can't find SPEC submissions for the Fuel, but here are some for their Origin using one of the choices in processors for the Fuel:

SGI SGI Origin 300 1X 600MHz R14000A 495 472

For comparison, here is the P4 at 3.06 GHz:
Dell Precision WorkStation 340 (3.06 GHz P4) 982 972

(The last two numbers are the peak and base results.)

The thing is... the R16k has (I was mistaken when I wrote about it earlier) LESS bandwidth (3.2 GB/s) than a current P4 (4.2 GB/s), less than 1/3 the clock speed, AND no better peak instructions per clock cycle... so the statement that it's more optimzed for performance at lower clock speeds doesn't make any sense.

What is more efficient? a 600mhz cpu which does 495/475 or a 3.06Ghz "monster" which does 982/972? It´s very clear that the MIPS architecture is more efficient. You have to compare mhz per mhz...Of course the statement that the MIPS is more optimized for performance at lower clock speeds makes sense. That´s RISC!
INTEL still hasn´t managed to come close to RISC cpu´s in efficiency. I just looked at spec.org: The ALPHA at 1.25Ghz does 1019/1365 in SPECfp2000! The RISC´s are still almost 3X more efficient that Intel´s P4 although the Itanium is catching up quickly.

Thalaxis

12-31-2002, 02:28 PM

Well, as I said... who cares?

Where will they be in a year? How far do you really think that the MIPS R16k will scale by the time the P4 reaches 4 GHz? 5? 6? There is a reason that they designed the processor the way that they did... which is why comparing MHz for MHz is pretty much pointless.

The R16k isn't a particularly aggressive design... but then, SGI has been working on transitioning from MIPS to Itanium2 for quite some time now, making the whole point pretty insignificant in the grand scheme of things.

beaker

12-31-2002, 08:53 PM

>> The R16k isn't a particularly aggressive design... but then, SGI has been working on transitioning from MIPS to Itanium2 for quite some time now, making the whole point pretty insignificant in the grand scheme of things.

Not quite, SGI made a statement a few years ago that they are supporting both platforms equally. Thats why they opened a new microprocessor design center in boston about a year ago. SGI's big business is their origin servers which can scale up to thousands of processors that MIPS chip is known to work in. The Itanium uses way too much power and puts out way too much heat for this kind of application. It isn't really ready yet to take over from mips on that side of things. SGI was smart with the Origin/Onyx 3xxx system by making it so modular with the bricks so they can pretty much use whatever processor they want with very little change to the overall architecture of the system.

Thalaxis

12-31-2002, 09:15 PM

Their big mistake was in cancelling their high-end MIPS processor designs and spinning off MIPS in order to focus on Merced before it was ready.

I think their long-term plan is still to switch, but they can't afford to ignore their existing customers. They're probably hoping that one of the next versions of Itanium will have low enough power consumption to be a feasible alternative, but given Intel's "we CAN cram more transistors in there, dammit!" methodology, that probably won't happen this year.

Modulok

12-31-2002, 09:57 PM

Ok, I'm no computer tech, so, in order for the laymen (like me) to understand the difference between a MIPS and say an Intel architecture I've come up with this stupid...yet understandable analogy....please correct me if I'm wrong anyone, because I probably am ;P

Say you have a pile of sand, this sand represents raw un-processed information. The processed information is when the sand has been moved into a bucket.

A conventional intel architecture moves the sand from the pile into the bucket with their processor, in this case a teaspoon. Now, they have a higher clock speed (scoops of sand into the bucket per second) than a MIPS, thus they look faster.

A MIPS processor though it moves data slower (in this case it makes less scoops per second) it moves more data (sand) in the end due to the fact that its processor instead of being a tablespoon is more like that of a large shovel. It has a lower clock speed (scoops per second) but it moves more data with less scoops, thus it actually processes more useable information in less time. (it fills the bucket up quicker, though its scooping slower)

This is just my stupid VERY BASIC analogy for understanding it. Please tell me I'm sorta right lol. :shrug:

-Modulok-

DotPainter

12-31-2002, 11:03 PM

Modulok: That is as good analogy as any:scream: These things can get pretty complicated, you know.

There are definitely trade-offs with either approach, ie: risc processors with large caches but lower clock speeds, versus high megahertz Pentiums that are unfortunately getting too hot and consume too much power to run much faster without a major redesign.

It will surely be interesting to see how Intel solves the power consumption and heat issues as it tries to break the 4.0 GHz barrier!

However, whenever I see spec scores alone, I still don't see why such a machine as the R16000 would be desirable. Maybe actually running say Maya or Lightwave on the box and comparing the performance (render times, OGL framerate) to a P4 3.0 with HT running the same apps would be better.....

arvid

01-01-2003, 09:47 PM

Originally posted by MacRonin
Here here!

Shoot the PC wankers!

;^p

http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/A1387A29AC1C2AE087256C5200611780/$file/PPC970_MPF2002.pdf

Mmmm...

eat my shorts, and my dust while you're at it

matty429

01-02-2003, 03:18 AM

Theres nothing worse in computers than an uninformed Mac User

Modulok

01-02-2003, 04:08 AM

Theres nothing worse in computers than an uninformed Mac User

Amen :beer:

-Modulok-

beaker

01-02-2003, 02:57 PM

>>Theres nothing worse in computers than an uninformed Mac User

He's not that uninformed, if you look at the SPEC tests, the current IBM Power4 1.3ghz beats a brand new P4 3ghz in FP perfromance(it runs neck on neck with the itanium 2 beta boxes), so I wouldn't doubt the 970 is going to kick some ass too. The p4 does beat both the itanium 2 and Power4 in INT, but its FP that matters in 3d.

Thalaxis

01-02-2003, 03:47 PM

Originally posted by beaker
>>Theres nothing worse in computers than an uninformed Mac User

He's not that uninformed, if you look at the SPEC tests, the current IBM Power4 1.3ghz beats a brand new P4 3ghz in FP perfromance(it runs neck on neck with the itanium 2 beta boxes), so I wouldn't doubt the 970 is going to kick some ass too. The p4 does beat both the itanium 2 and Power4 in INT, but its FP that matters in 3d.

And yet if you look at the performance data for both, things don't look so good for the PPC970. Remember, it's not a Power4; it doesn't have a 128 MB 2nd level cache, and it doesn't have a 100 GB/s (no, I'm not exaggerating) system bus.

According to the data the IBM divulged, the performance of the PPC970 measured using SPECcpu2000 is right between the performance of a 2.8 GHz P4 and a 3.06 GHz P4.

As for how Intel is going to hit 4 GHz: .09 micron strained silicon
fabs should do the trick.

Their engineers claim that the P4's architecture will reach 10 GHz. That will take a while, and probably at least .065 micron fabs.

beaker

01-02-2003, 04:52 PM

yea, my point was just that he's not an uninformed mac user. Even if the 970 is close to the power4 then we are in good hands.

matty429

01-02-2003, 05:59 PM

That sort of pdf is and will always be biased...no matter who its from...besides it probably will never happen...and if it does you can count on Crapple to make it happen very late...

The uninformed part ..pertains to him saying shoot the pc users....
If you did that then how stable would the mac be...It couldn't adopt all of the x86 tech...like agp or ddr ram, years after pc users hammered all the bugs out for them...

If you want to go the way of floating poit....then you'd have to include AMD in comparrison also....

Thalaxis

01-02-2003, 06:46 PM

It looks like Intel will retain the lead in floating point on the desktop for the foreseeable future, from what I can tell; it seems that AMD will be hard pressed to match even the Northwood as it scales up in clock speed, and Intel's roadmap has the Prescott launching in the 2nd half of this year. According to the Intel dude (in an interview), the Prescott has enough changes in it that they will market it as a P5, even though it's based on the same architecture.

As to what those changes are, other than the .09 micron strained silicon process, Intel's keeping them under their hat. From what I understand the project is going quite well, though.

AMD will have an advantage in SMP and size-constrained applications, and in system cost. The integrated northbridge takes one chip off of the motherboard, and also makes adding processors easier for everyone involved, while improving the processor's ability to scale when you do.

That's why one SledgeHammer has 5.4 GB/s of system bandwidth, but a quad-SledgeHammer has 21.6 GB/s of system bandwidth. Of course that's peak, and hence not achievable, but at least it's not pure marketing BS (for once :shame: ).