Array
08-19-2004, 09:49 AM
http://www.theregister.co.uk/2004/08/18/dual-cores_detailed/
Interesting....
Interesting....
View Full Version : New powerbooks to sport dual core G4 processors?
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Beamtracer
08-19-2004, 11:52 AM
Amazing that Freescale (Motorola) is developing a dual core G4 processor. It would have to be for Apple's laptops. I can't see where else they would go, as Freescale's other clients make imbedded devices rather than computers. It will give Apple a choice of processors again. Either a 64-bit dual core G4 from Freescale, or a 64-bit G5 from IBM.
onlooker
08-19-2004, 06:07 PM
It's kinda old news, but the register, and rumor mongers are the only ones that think this processor is for consumer computers. Most people think that the design is not engineered for PC's, and not capable of running such things. But Who knows? Maybe, but I doubt it as well.
edited post from another forum
I'm getting the feeling that this dual core is all about bringing a competitor to bear for the MIPS-based dual-core Broadcom 1250, and the processor may not even be applicable to personal computer usage.
edited post from another forum
I'm getting the feeling that this dual core is all about bringing a competitor to bear for the MIPS-based dual-core Broadcom 1250, and the processor may not even be applicable to personal computer usage.
Thalaxis
08-19-2004, 06:46 PM
It's kinda old news, but the register, and rumor mongers are the only ones that think this processor is for consumer computers. Most people think that the design is not engineered for PC's, and not capable of running such things. But Who knows? Maybe, but I doubt it as well.
Well, that never stopped Apple from using G4's before. The G4's biggest buyers were using it in networking equipment. Ericcson announced that they were using the 1 GHz G4+ long before Apple did, for example.
Still, beggars can't be choosers... unless either IBM gets their 970fx production problems resolved first or Apple gives up on the PPC entirely, it's probably going to be their best interim option.
Well, that never stopped Apple from using G4's before. The G4's biggest buyers were using it in networking equipment. Ericcson announced that they were using the 1 GHz G4+ long before Apple did, for example.
Still, beggars can't be choosers... unless either IBM gets their 970fx production problems resolved first or Apple gives up on the PPC entirely, it's probably going to be their best interim option.
mummey
08-19-2004, 06:49 PM
Still, beggars can't be choosers... unless either IBM gets their 970fx production problems resolved first or Apple gives up on the PPC entirely, it's probably going to be their best interim option.
The PPC970 is arguably the best desktop processor out there and you want Apple to get rid of it??? Please tell me I misread that!
The PPC970 is arguably the best desktop processor out there and you want Apple to get rid of it??? Please tell me I misread that!
Thalaxis
08-19-2004, 06:54 PM
The PPC970 is arguably the best desktop processor out there and you want Apple to get rid of it??? Please tell me I misread that!
The best? Only if you define "best" as "what Apple picked". By most standards, it's outclassed.
The best? Only if you define "best" as "what Apple picked". By most standards, it's outclassed.
mummey
08-19-2004, 07:33 PM
The best? Only if you define "best" as "what Apple picked". By most standards, it's outclassed.
I'm not an Apple Fanboy. I'm an IBM fanboy. ;)
and outclassed? Outclassed doing what? Running Windows???
I'm not an Apple Fanboy. I'm an IBM fanboy. ;)
and outclassed? Outclassed doing what? Running Windows???
Thalaxis
08-19-2004, 07:47 PM
I'm not an Apple Fanboy. I'm an IBM fanboy. ;)
Don't go there... I grew up in an "I've Been Moved" family... knowing what sort of company IBM was before Intel, MS, Compaq, and DEC beat the snot out of them doesn't exactly endear me to them, and the way that my mother ended up leaving doesn't fill me with either confidence or love.
Basically, I don't think Lou Gershener's enema was thorough enough... he left too many of the old-timers in charge.
and outclassed? Outclassed doing what? Running Windows???
Almost everything, actually.
And let's be real here. IBM is struggling to hit 2.5 GHz with marketable yields with a processor made with a 20 stage pipeline on a 90 nm, SoI process.
Intel hit 3.4 GHz with more quarterly units sold than IBM's total capacity using a 20 stage pipeline and a 130 nm process.
AMD reached 2.4 GHz with a 15-stage pipeline and a 130 nm, SoI process.
Even Motorola is shipping more processors than IBM now. (Talk about adding insult to injury, ouch!)
Don't go there... I grew up in an "I've Been Moved" family... knowing what sort of company IBM was before Intel, MS, Compaq, and DEC beat the snot out of them doesn't exactly endear me to them, and the way that my mother ended up leaving doesn't fill me with either confidence or love.
Basically, I don't think Lou Gershener's enema was thorough enough... he left too many of the old-timers in charge.
and outclassed? Outclassed doing what? Running Windows???
Almost everything, actually.
And let's be real here. IBM is struggling to hit 2.5 GHz with marketable yields with a processor made with a 20 stage pipeline on a 90 nm, SoI process.
Intel hit 3.4 GHz with more quarterly units sold than IBM's total capacity using a 20 stage pipeline and a 130 nm process.
AMD reached 2.4 GHz with a 15-stage pipeline and a 130 nm, SoI process.
Even Motorola is shipping more processors than IBM now. (Talk about adding insult to injury, ouch!)
mummey
08-19-2004, 07:58 PM
Don't go there... I grew up in an "I've Been Moved" family... knowing what sort of company IBM was before Intel, MS, Compaq, and DEC beat the snot out of them doesn't exactly endear me to them, and the way that my mother ended up leaving doesn't fill me with either confidence or love.
Basically, I don't think Lou Gershener's enema was thorough enough... he left too many of the old-timers in charge.
WHOH! Someone took my post a little too personally. I would argue that the GHz myth but you beat me to it. So instead I'll argue your definition of processor.
Technically Texas Instruments makes more processors than any of them. In reality the only one's they make for computers are Sun Ultrasparcs. Somehow I would guess more Motorola processors end up in phones than computers.
DEC didn't beat the snot out of anyone. They were just opportunistic with the Alpha and even then they still screwed up and had to get bought by Compaq to stay alive. Intel and compaq were they one's that drove them out of the PC market (Microchannel anyone?)
IBM is an evil meglomanical company that treats its employees like dirt sometimes. Unlike other companies though, they make no attempts to hide it anymore. :)
Edit: On a related note, one would think Apple would learn a thing or two about overheating laptop batteries (https://depot.info.apple.com/batteryexchange/index.html) by now.
Basically, I don't think Lou Gershener's enema was thorough enough... he left too many of the old-timers in charge.
WHOH! Someone took my post a little too personally. I would argue that the GHz myth but you beat me to it. So instead I'll argue your definition of processor.
Technically Texas Instruments makes more processors than any of them. In reality the only one's they make for computers are Sun Ultrasparcs. Somehow I would guess more Motorola processors end up in phones than computers.
DEC didn't beat the snot out of anyone. They were just opportunistic with the Alpha and even then they still screwed up and had to get bought by Compaq to stay alive. Intel and compaq were they one's that drove them out of the PC market (Microchannel anyone?)
IBM is an evil meglomanical company that treats its employees like dirt sometimes. Unlike other companies though, they make no attempts to hide it anymore. :)
Edit: On a related note, one would think Apple would learn a thing or two about overheating laptop batteries (https://depot.info.apple.com/batteryexchange/index.html) by now.
Thalaxis
08-19-2004, 08:41 PM
WHOH! Someone took my post a little too personally. I would argue that the GHz myth but you beat me to it. So instead I'll argue your definition of processor.
My commentary was intended to address their fabrication problems. The whole point behind increasing the length of the pipeline is to allow for higher clock speeds, in order to make up for the branch mispredict penalties and increased latencies. IBM basically added the latencies and branch mispredict penalties without offsetting them with clock speed, even though they threw a LOT more technology at it than Intel and AMD did.
In other words, they dropped the ball -- and they're still struggling to get production up?!
I was really just venting at IBM a bit, more than anything else, putzes that they are. It's amazing that a company with that much engineering talent can do so little to capitalize on it.
Technically Texas Instruments makes more processors than any of them. In reality the only one's they make for computers are Sun Ultrasparcs. Somehow I would guess more Motorola processors end up in phones than computers.
Don't forget networking products. The G4 family is very popular with the telco vendors like Ericcson and Cisco.
DEC didn't beat the snot out of anyone. They were just opportunistic with the Alpha and even then they still screwed up and had to get bought by Compaq to stay alive. Intel and compaq were they one's that drove them out of the PC market (Microchannel anyone?)
That was later. Before that they launched the VAX which stole a huge amount of market share from IBM, because it cost 1/10 as much as one of IBM's mainframes, and didn't have IBM's assinine pricing associated with it, in that you didn't have to pay IBM $40,000 to have an engineer come out and flip a switch to speed your system up (that's not a joke).
Of course, DEC followed up their success with dazzlingly stupid decision (stifling the Alpha among them), which lead to their decline, but they did help Compaq, Intel, and MS (which got snuffed out by AT&T -- I have some amusing stories about working there) beat the stuffing out of IBM for a while.
IBM is an evil meglomanical company that treats its employees like dirt sometimes. Unlike other companies though, they make no attempts to hide it anymore. :)
True. I think they gave up on that idea when they bought Lotus, and every Lotus employee simply left rather than work for Big Blue. They also do some amazingly stupid things, though; they actually had a PDA design in their think tanks before Apple even mentioned the Newton publicly... and never actually sold one, because they didn't bother making it.
That's also how they killed their dominance in the PC market... they just decided not to make a 486 because it was too powerful for the desktop market. So Compaq ate them alive.
Edit: On a related note, one would think Apple would learn a thing or two about overheating laptop batteries (https://depot.info.apple.com/batteryexchange/index.html) by now.
Sheesh... it's sometimes hard to tell with Apple whether that was a manufacturing problem, or a result of an under-funded QA department. :D
My commentary was intended to address their fabrication problems. The whole point behind increasing the length of the pipeline is to allow for higher clock speeds, in order to make up for the branch mispredict penalties and increased latencies. IBM basically added the latencies and branch mispredict penalties without offsetting them with clock speed, even though they threw a LOT more technology at it than Intel and AMD did.
In other words, they dropped the ball -- and they're still struggling to get production up?!
I was really just venting at IBM a bit, more than anything else, putzes that they are. It's amazing that a company with that much engineering talent can do so little to capitalize on it.
Technically Texas Instruments makes more processors than any of them. In reality the only one's they make for computers are Sun Ultrasparcs. Somehow I would guess more Motorola processors end up in phones than computers.
Don't forget networking products. The G4 family is very popular with the telco vendors like Ericcson and Cisco.
DEC didn't beat the snot out of anyone. They were just opportunistic with the Alpha and even then they still screwed up and had to get bought by Compaq to stay alive. Intel and compaq were they one's that drove them out of the PC market (Microchannel anyone?)
That was later. Before that they launched the VAX which stole a huge amount of market share from IBM, because it cost 1/10 as much as one of IBM's mainframes, and didn't have IBM's assinine pricing associated with it, in that you didn't have to pay IBM $40,000 to have an engineer come out and flip a switch to speed your system up (that's not a joke).
Of course, DEC followed up their success with dazzlingly stupid decision (stifling the Alpha among them), which lead to their decline, but they did help Compaq, Intel, and MS (which got snuffed out by AT&T -- I have some amusing stories about working there) beat the stuffing out of IBM for a while.
IBM is an evil meglomanical company that treats its employees like dirt sometimes. Unlike other companies though, they make no attempts to hide it anymore. :)
True. I think they gave up on that idea when they bought Lotus, and every Lotus employee simply left rather than work for Big Blue. They also do some amazingly stupid things, though; they actually had a PDA design in their think tanks before Apple even mentioned the Newton publicly... and never actually sold one, because they didn't bother making it.
That's also how they killed their dominance in the PC market... they just decided not to make a 486 because it was too powerful for the desktop market. So Compaq ate them alive.
Edit: On a related note, one would think Apple would learn a thing or two about overheating laptop batteries (https://depot.info.apple.com/batteryexchange/index.html) by now.
Sheesh... it's sometimes hard to tell with Apple whether that was a manufacturing problem, or a result of an under-funded QA department. :D
onlooker
08-19-2004, 08:46 PM
I think you missed my pointy completely.
this dual core is all about bringing a competitor to bear for the MIPS-based dual-core Broadcom 1250, and the processor may not even be applicable to personal computer usage.
That was all I was trying to note here.
this dual core is all about bringing a competitor to bear for the MIPS-based dual-core Broadcom 1250, and the processor may not even be applicable to personal computer usage.
That was all I was trying to note here.
Thalaxis
08-19-2004, 08:57 PM
I think you missed my pointy completely.
That was all I was trying to note here.
I didn't miss your point all, I was agreeing with you... and pointing out that that is only business as usual for Motorola, hardly anything new.
That was all I was trying to note here.
I didn't miss your point all, I was agreeing with you... and pointing out that that is only business as usual for Motorola, hardly anything new.
richcz3
08-19-2004, 10:03 PM
Thalaxis The whole IBM to the rescue then struggle to get to 3GHz by 4th Qtr really shocked the hell out of me. I bet that revelation really PO'd Steve Jobs. He could finally dump floundering Motorola and engage in the GHz race. That's not going to happen any time soon and this is what forced the water cooled 2.5GHz systems. OUCH.
richcz3
richcz3
Thalaxis
08-19-2004, 10:41 PM
Thalaxis The whole IBM to the rescue then struggle to get to 3GHz by 4th Qtr really shocked the hell out of me. I bet that revelation really PO'd Steve Jobs. He could finally dump floundering Motorola and engage in the GHz race. That's not going to happen
Most poeple (mac fans in particular) wanted to believe that IBM would be Apple's white knight primarily because of the fact that Apple chose them, and they aren't Intel.
I was expecting it to fall short on clock speed and performance relative to Apple's vaunted claims, but I also expected IBM to be able to supply plenty of them, with low enough power consumption to be viable laptop processors.
Most poeple (mac fans in particular) wanted to believe that IBM would be Apple's white knight primarily because of the fact that Apple chose them, and they aren't Intel.
I was expecting it to fall short on clock speed and performance relative to Apple's vaunted claims, but I also expected IBM to be able to supply plenty of them, with low enough power consumption to be viable laptop processors.
onlooker
08-19-2004, 11:14 PM
I thought when IBM, and Apple co_announced 3GHz for this year at last years WWDC they must have had good reason to believe they would do it, and I believed it then. But as the clock ticked closer to WWDC, and rumors started flying around I too was not believing that 3GHz was going to make the deadline, but it's getting ridiculously depressing to be a Mac user again. Reminds me of the Motorola days. I think I'm getting out soon. :banghead:
Beamtracer
08-20-2004, 12:03 AM
The delays with the IBM "G5" processor are due only to one thing... a new 90nanometer fabrication plant.
IBM have had some teething difficulties getting their new Fishkill processor factory running at the new smaller 90nm size. It has nothing to do with the actual processors being produced at the plant.
The G5 is a wonderful processor. As Apple's new developer tools gain more penetration, we'll see more apps come out optimized for the G5.
Keep an eye out for Luxology's new 3D applications. No legacy code or prior baggage. These apps should set a good example of what the G5 is capable of for 3D work.
IBM have had some teething difficulties getting their new Fishkill processor factory running at the new smaller 90nm size. It has nothing to do with the actual processors being produced at the plant.
The G5 is a wonderful processor. As Apple's new developer tools gain more penetration, we'll see more apps come out optimized for the G5.
Keep an eye out for Luxology's new 3D applications. No legacy code or prior baggage. These apps should set a good example of what the G5 is capable of for 3D work.
mattin
08-20-2004, 03:00 AM
By most standards, it's outclassed.
yes and because this is true, virginia tech build the third fastest supercomputer with G5s. but hey, your are the pro here... (http://cgtalk.com/showpost.php?p=1517099&postcount=83)
yes and because this is true, virginia tech build the third fastest supercomputer with G5s. but hey, your are the pro here... (http://cgtalk.com/showpost.php?p=1517099&postcount=83)
silvergun
08-20-2004, 03:44 AM
Don't bother listening to Thalaxis on this outclassed thing, he said this kind of thing on a previous post and I proved him wrong then. And they say Steve Jobs lives in a reality distorted world. :thumbsup:
mummey
08-20-2004, 03:53 AM
Most poeple (mac fans in particular) wanted to believe that IBM would be Apple's white knight primarily because of the fact that Apple chose them, and they aren't Intel.
You seem to have selective memory. Apple 'chose' the IBM processors after Motorola couldn't get the G4 above 1GHz. Apple even waited a year and tried to use Dual processors on the G4 as a stop gap. IBM DID come the rescue with the PPC970 because Apple had fallen so far behind in speed thanks to Motorola. Don't forget, it was Motorola that decided to stop working with IBM on PowerPC processors, not the other way around.
-b
mattin: thank you for the info. While its been a year or two since I've taken Microprocessor design (Shameless Plug: EECS 370 at U of M), I was pretty sure what was coming out of his posts was almost completely BS.
You seem to have selective memory. Apple 'chose' the IBM processors after Motorola couldn't get the G4 above 1GHz. Apple even waited a year and tried to use Dual processors on the G4 as a stop gap. IBM DID come the rescue with the PPC970 because Apple had fallen so far behind in speed thanks to Motorola. Don't forget, it was Motorola that decided to stop working with IBM on PowerPC processors, not the other way around.
-b
mattin: thank you for the info. While its been a year or two since I've taken Microprocessor design (Shameless Plug: EECS 370 at U of M), I was pretty sure what was coming out of his posts was almost completely BS.
Thalaxis
08-20-2004, 07:07 AM
yes and because this is true, virginia tech build the third fastest supercomputer with G5s. but hey, your are the pro here... (http://cgtalk.com/showpost.php?p=1517099&postcount=83)
Let's see how many mac uses run LINPACK... and in any case, that system isn't even listed in the current top 500 edition. Odd that, eh?
Let's see how many mac uses run LINPACK... and in any case, that system isn't even listed in the current top 500 edition. Odd that, eh?
Thalaxis
08-20-2004, 07:08 AM
Don't bother listening to Thalaxis on this outclassed thing, he said this kind of thing on a previous post and I proved him wrong then. And they say Steve Jobs lives in a reality distorted world. :thumbsup:
No, you didn't.
No, you didn't.
Thalaxis
08-20-2004, 07:10 AM
You seem to have selective memory. Apple 'chose' the IBM processors after Motorola couldn't get the G4 above 1GHz. Apple even waited a year and tried to use Dual processors on the G4 as a stop gap. IBM DID come the rescue with the PPC970 because Apple had fallen so far behind in speed thanks to Motorola. Don't forget, it was Motorola that decided to stop working with IBM on PowerPC processors, not the other way around.
No, you just have trouble with reading comprehension.
No, you just have trouble with reading comprehension.
Thalaxis
08-20-2004, 07:27 AM
I thought when IBM, and Apple co_announced 3GHz for this year at last years WWDC they must have had good reason to believe they would do it, and I believed it then. But as the clock ticked closer to WWDC, and rumors started flying around I too was not believing that 3GHz was going to make the deadline, but it's getting ridiculously depressing to be a Mac user again. Reminds me of the Motorola days. I think I'm getting out soon. :banghead:
What was really funny was the discussions about that claim on the tech forums. Some people were amused by the fact that IBM couldn't hit 3 GHz already with all the technology that they threw at it.
They're also losing money hand over fist in microelectronics. They were getting pretty close to $2 billion in losses before the decided to conceal their microelectronics division inside their server division. The resultant cost-cutting probably didn't help their design efforts any.
What was really funny was the discussions about that claim on the tech forums. Some people were amused by the fact that IBM couldn't hit 3 GHz already with all the technology that they threw at it.
They're also losing money hand over fist in microelectronics. They were getting pretty close to $2 billion in losses before the decided to conceal their microelectronics division inside their server division. The resultant cost-cutting probably didn't help their design efforts any.
mummey
08-20-2004, 10:04 AM
Thalaxis: In case you haven't hoticed. You are giving statements that no one has heard before. If you want to get our attention, have the resources to back them up. Otherwise you are just feeding us BS.
-b
-b
mattin
08-20-2004, 12:13 PM
Let's see how many mac uses run LINPACK... and in any case, that system isn't even listed in the current top 500 edition. Odd that, eh?LOL! Yes very odd. Maybe they rebuild the cluster with more powerful (2.5ghz) Xserves? :D :rolleyes:
Please Thalaxis please stop flaming!
We don't need flamer here, find a hobby, fishing for example!
Every time i find one of your posts i realize that you still don`t now what you are talking about. So i have to show you the facts. it is a lot of work, i have to find the sources again and i have to check my english (because it is not very good), it takes a lot of time. and time is money. So please stop flaming.
If you don't care about me, think of that:
Every time your flame god kills a kitten please think of the kitten!
So here is my last try to save kitten:
Thalaxis:
Almost everything, actually.
And let's be real here. IBM is struggling to hit 2.5 GHz with marketable yields with a processor made with a 20 stage pipeline on a 90 nm, SoI process.
Intel hit 3.4 GHz with more quarterly units sold than IBM's total capacity using a 20 stage pipeline and a 130 nm process.
AMD reached 2.4 GHz with a 15-stage pipeline and a 130 nm, SoI process.
Even Motorola is shipping more processors than IBM now. (Talk about adding insult to injury, ouch!) Again you demonstrate utter lack of knowledge about CPU-Design (see the other thread -> http://www.cgtalk.com/showpost.php?p=1517099&postcount=83 ) by defining a CPU solely through its Pipeline depth and MHz.
Criteria like "IPC" escape you, which on average is the basic measure together with MHz of how much a CPU can actually do.
To sum it up for you: The criticism of the P4-Design didn't revolve solely around its Pipeline-Depth, but around the "long and narrow"-Design: It simply lacks enough execution units to get much stuff done per cycle. And the penalty when all Units are occupied is much greater than with slower-clocked CPUs with more execution units, because a design like the P4s depends almost completely on moving a continuous stream of instructions FAST through the CPU, it simply can't do anything when all Units are occupied. The P970 however is a synthesis of the G4-Design (lots of execution Units, even MORE than the G4 (2 FPUs)) and the P4 (long pipeline, high clock). Its design is "wide and fast". This means that Execution rarely will come to a halt because all Units are occupied. The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time. If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
So while the P4s potential is definately maxed out and with code compiled with current compilers it's already running at maximum speed (only stuff like SSE3 and optimizing for the new larger caches actually allows for some more improvement) the P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!) for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want". The P4s SIMD is already maxed out and running at full speed with most applications right now, the G4s and P970s SIMD sits mostly idle with the occasional Altivec-optimized app popping by for some action!
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps. And when the Prescott was released yields were so bad that it was in fact a paper launch, like Intel has done it so often before. When Intel-sweetheart Dell throws the Prescott out of its line-up because they just don't get enough of them for a whole product line you definately know what the deal is.
AMD also kept moving their 90nm launch further and further back and are now the only one that still doesn't ship any 90nm-CPU (and no, the "revenue launch" of the Oakville now is a mere joke! It's just for the books, they don't actually ship anything!).
So yes, the yields of the 90nm-P970 aren't as good as IBM hoped, but for a change it's no propaganda when Steve Jobs says "the whole industry has hit the wall" - he's completely right about that, which anybody can confirm that follows the industry...
Intel is starting to get their 90nm-problems fixed, but at what cost? The P4 is leaking so much current due to lack of SOI that it must be the first CPU on the planet that eats MORE power than its larger-scale predecessor at the same clock!
So yes, AMD reached 2.4 GHz with 130nm and Intel 3.4 GHz with 130 nm. However, the P4-Design was built for high clockspeed and can't possibly be compared to an Execution-unit-loaded-CPU like the P970. The Opteron, while also featuring much less execttion units than the P970 is not that much different to an Athlon with SSE2, x86-64, a memory controller and larger cache. AMD reached 2.17 GHz in August 2002 with the Athlon 2600+. Now, exactly 2 years later, they're at 2.4 GHz. Sorry, but i really don't see any huge clock-scaling there!
IBM just doesn't want to make a faster version of the 130nm P970 i assume. It would just eat too much power for apple and IBM to tolerate, although it would technically probably be possible. Intel and AMD just adjust the maximum power dissipation and temperature accordingly and leave the difficult cooling-part to the system builders! IBM rather focusses their resources on getting their 90nm-act together, which is definately the better and more promising approach. The 130nm 3.4 GHz P4EE is a horrible kludge that Intel just threw together hastily BECAUSE Prescott was too late! They had no other choice to match the power of an integrated memory controller in the Athlon-FX because Prescott simply wasn't there!
Dito the 2.4 GHz Opteron and Athlon-FX (can these actually be bought in volume anywhere? Like as in: Is there a system builder selling 200.000-350.000 of these per quarter, which is what apple puts through in P970s?), they're just makeshift because AMDs 90nm-CPUs are also delayed.
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
In case you haven't noticed: the 970FX is so far the only 90nm-CPU that eats LESS power than its 130nm-predecessor, like it's supposed to be...
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube! ;)
Please Thalaxis please stop flaming!
We don't need flamer here, find a hobby, fishing for example!
Every time i find one of your posts i realize that you still don`t now what you are talking about. So i have to show you the facts. it is a lot of work, i have to find the sources again and i have to check my english (because it is not very good), it takes a lot of time. and time is money. So please stop flaming.
If you don't care about me, think of that:
Every time your flame god kills a kitten please think of the kitten!
So here is my last try to save kitten:
Thalaxis:
Almost everything, actually.
And let's be real here. IBM is struggling to hit 2.5 GHz with marketable yields with a processor made with a 20 stage pipeline on a 90 nm, SoI process.
Intel hit 3.4 GHz with more quarterly units sold than IBM's total capacity using a 20 stage pipeline and a 130 nm process.
AMD reached 2.4 GHz with a 15-stage pipeline and a 130 nm, SoI process.
Even Motorola is shipping more processors than IBM now. (Talk about adding insult to injury, ouch!) Again you demonstrate utter lack of knowledge about CPU-Design (see the other thread -> http://www.cgtalk.com/showpost.php?p=1517099&postcount=83 ) by defining a CPU solely through its Pipeline depth and MHz.
Criteria like "IPC" escape you, which on average is the basic measure together with MHz of how much a CPU can actually do.
To sum it up for you: The criticism of the P4-Design didn't revolve solely around its Pipeline-Depth, but around the "long and narrow"-Design: It simply lacks enough execution units to get much stuff done per cycle. And the penalty when all Units are occupied is much greater than with slower-clocked CPUs with more execution units, because a design like the P4s depends almost completely on moving a continuous stream of instructions FAST through the CPU, it simply can't do anything when all Units are occupied. The P970 however is a synthesis of the G4-Design (lots of execution Units, even MORE than the G4 (2 FPUs)) and the P4 (long pipeline, high clock). Its design is "wide and fast". This means that Execution rarely will come to a halt because all Units are occupied. The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time. If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
So while the P4s potential is definately maxed out and with code compiled with current compilers it's already running at maximum speed (only stuff like SSE3 and optimizing for the new larger caches actually allows for some more improvement) the P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!) for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want". The P4s SIMD is already maxed out and running at full speed with most applications right now, the G4s and P970s SIMD sits mostly idle with the occasional Altivec-optimized app popping by for some action!
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps. And when the Prescott was released yields were so bad that it was in fact a paper launch, like Intel has done it so often before. When Intel-sweetheart Dell throws the Prescott out of its line-up because they just don't get enough of them for a whole product line you definately know what the deal is.
AMD also kept moving their 90nm launch further and further back and are now the only one that still doesn't ship any 90nm-CPU (and no, the "revenue launch" of the Oakville now is a mere joke! It's just for the books, they don't actually ship anything!).
So yes, the yields of the 90nm-P970 aren't as good as IBM hoped, but for a change it's no propaganda when Steve Jobs says "the whole industry has hit the wall" - he's completely right about that, which anybody can confirm that follows the industry...
Intel is starting to get their 90nm-problems fixed, but at what cost? The P4 is leaking so much current due to lack of SOI that it must be the first CPU on the planet that eats MORE power than its larger-scale predecessor at the same clock!
So yes, AMD reached 2.4 GHz with 130nm and Intel 3.4 GHz with 130 nm. However, the P4-Design was built for high clockspeed and can't possibly be compared to an Execution-unit-loaded-CPU like the P970. The Opteron, while also featuring much less execttion units than the P970 is not that much different to an Athlon with SSE2, x86-64, a memory controller and larger cache. AMD reached 2.17 GHz in August 2002 with the Athlon 2600+. Now, exactly 2 years later, they're at 2.4 GHz. Sorry, but i really don't see any huge clock-scaling there!
IBM just doesn't want to make a faster version of the 130nm P970 i assume. It would just eat too much power for apple and IBM to tolerate, although it would technically probably be possible. Intel and AMD just adjust the maximum power dissipation and temperature accordingly and leave the difficult cooling-part to the system builders! IBM rather focusses their resources on getting their 90nm-act together, which is definately the better and more promising approach. The 130nm 3.4 GHz P4EE is a horrible kludge that Intel just threw together hastily BECAUSE Prescott was too late! They had no other choice to match the power of an integrated memory controller in the Athlon-FX because Prescott simply wasn't there!
Dito the 2.4 GHz Opteron and Athlon-FX (can these actually be bought in volume anywhere? Like as in: Is there a system builder selling 200.000-350.000 of these per quarter, which is what apple puts through in P970s?), they're just makeshift because AMDs 90nm-CPUs are also delayed.
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
In case you haven't noticed: the 970FX is so far the only 90nm-CPU that eats LESS power than its 130nm-predecessor, like it's supposed to be...
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube! ;)
Thalaxis
08-20-2004, 05:35 PM
Every time i find one of your posts i realize that you still don`t now what you are talking about. So i have to show you the facts. it is a lot of work, i have to find the sources again and i have to check my english (because it is not very good), it takes a lot of time. and time is money. So please stop flaming.
Your arrogance is unbecoming, since you really don't know anything.
Again you demonstrate utter lack of knowledge about CPU-Design (see the other thread -> http://www.cgtalk.com/showpost.php?p=1517099&postcount=83 ) by defining a CPU solely through its Pipeline depth and MHz.
I was characterizing manufacturing, not the processor architecture.
Criteria like "IPC" escape you, which on average is the basic measure together with MHz of how much a CPU can actually do.
No, it doesn't -- I wasn't talking about processor performance.
To sum it up for you: The criticism of the P4-Design didn't revolve solely around its Pipeline-Depth, but around the "long and narrow"-Design: It simply lacks enough execution units to get much stuff done per cycle. And the penalty when all Units are occupied is much greater than with slower-clocked CPUs with more execution units,
The units are never all occupied. The problem is exactly the opposite, and the processor designers work hard to utilize idle resources.
The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time.
That doesn't help performance in the real world any, because it's very difficult to mix scalar and SIMD instructions to begin with. On top of that, altivec doesn't even support double precision anyway.
If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
Yes, and it can do double-precision arithmetic in SIMD, and has a dedicated load/store unit to keep it fed.
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual.
So while the P4s potential is definately maxed out and with code compiled with current compilers it's already running at maximum speed
No, it isn't.
(only stuff like SSE3 and optimizing for the new larger caches actually allows for some more improvement)
If anything you said earlier had any merit, larger caches wouldn't help.
the P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!)
SSE2 isn't only for SIMD; it also provides a flat register model to circumvent the x87 stack.
for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want".
Too bad it doesn't work that way in the real world... SIMD isn't a general-purpose method of computing, it requires specially designed AND optimized code.
The P4s SIMD is already maxed out and running at full speed with most applications right now
Pure fallacy.
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps.
According to their roadmaps they were three months late.
AMD also kept moving their 90nm launch further and further back and are now the only one that still doesn't ship any 90nm-CPU (and no, the "revenue launch" of the Oakville now is a mere joke! It's just for the books, they don't actually ship anything!).
It means that they're selling processors to system builders.
So yes, the yields of the 90nm-P970 aren't as good as IBM hoped, but for a change it's no propaganda when Steve Jobs says "the whole industry has hit the wall" - he's completely right about that, which anybody can confirm that follows the industry...
Anyone who's been paying attention can tell you that the industry has not hit the wall.
Intel is starting to get their 90nm-problems fixed, but at what cost? The P4 is leaking so much current due to lack of SOI that it must be the first CPU on the planet that eats MORE power than its larger-scale predecessor at the same clock!
It's because of physics, not because they don't use SoI. SoI helps reduce leakage in some areas, but the tradeoff is higher wafer costs, and higher defect densities. Also consider the fact that Prescott has close to 3x as many transistors as Northwood.
So yes, AMD reached 2.4 GHz with 130nm and Intel 3.4 GHz with 130 nm. However, the P4-Design was built for high clockspeed and can't possibly be compared to an Execution-unit-loaded-CPU like the P970. The Opteron, while also featuring much less execttion units than the P970 is not that much different to an Athlon with SSE2, x86-64, a memory controller and larger cache.
The G5 doesn't have as much of a lead in execution resources as you think it does.
AMD reached 2.17 GHz in August 2002 with the Athlon 2600+. Now, exactly 2 years later, they're at 2.4 GHz. Sorry, but i really don't see any huge clock-scaling there!
They got to 2.4 GHz on 130 nm, while IBM is barely exceeding that with 90 nm. How hard is that to understand?
IBM just doesn't want to make a faster version of the 130nm P970 i assume.
It would just eat too much power for apple and IBM to tolerate, although it would technically probably be possible.
Die size is a huge motivating factor. IBM's priority is to make it smaller. That's why they didn't add any cache when they transitioned to 90nm. Smaller dies are less costly to produce, and they're using a very expensive fab process to make the PPC970.
The 130nm 3.4 GHz P4EE is a horrible kludge that Intel just threw together hastily BECAUSE Prescott was too late! They had no other choice to match the power of an integrated memory controller in the Athlon-FX because Prescott simply wasn't there!
They probably understimated AMD. I think the only reason that the P4EE exists at all was to counter the Athlon64, but it wasn't a hack; it was a core that had been in production for a long time, with a different market.
Dito the 2.4 GHz Opteron and Athlon-FX (can these actually be bought in volume anywhere? Like as in: Is there a system builder selling 200.000-350.000 of these per quarter, which is what apple puts through in P970s?), they're just makeshift because AMDs 90nm-CPUs are also delayed.
They're selling very well, based on the sales data. Also keep in mind the majority of Apple's sales recently have been laptops, and that they're still supply-limited on G5's.
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
Then maybe you should try applying your own standards, especially given how many execution resources Itanium has (and only a 7-stage pipeline, clearly not built for clock speed).
In case you haven't noticed: the 970FX is so far the only 90nm-CPU that eats LESS power than its 130nm-predecessor, like it's supposed to be...
That's not even accurate. AMD's 90nm design is lower power than their 130 nm design, and Intel has one also. P4 isn't Intel's only mainstream product, and I'm not talking about Celeron.
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube! ;)
Not always.
Your arrogance is unbecoming, since you really don't know anything.
Again you demonstrate utter lack of knowledge about CPU-Design (see the other thread -> http://www.cgtalk.com/showpost.php?p=1517099&postcount=83 ) by defining a CPU solely through its Pipeline depth and MHz.
I was characterizing manufacturing, not the processor architecture.
Criteria like "IPC" escape you, which on average is the basic measure together with MHz of how much a CPU can actually do.
No, it doesn't -- I wasn't talking about processor performance.
To sum it up for you: The criticism of the P4-Design didn't revolve solely around its Pipeline-Depth, but around the "long and narrow"-Design: It simply lacks enough execution units to get much stuff done per cycle. And the penalty when all Units are occupied is much greater than with slower-clocked CPUs with more execution units,
The units are never all occupied. The problem is exactly the opposite, and the processor designers work hard to utilize idle resources.
The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time.
That doesn't help performance in the real world any, because it's very difficult to mix scalar and SIMD instructions to begin with. On top of that, altivec doesn't even support double precision anyway.
If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
Yes, and it can do double-precision arithmetic in SIMD, and has a dedicated load/store unit to keep it fed.
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual.
So while the P4s potential is definately maxed out and with code compiled with current compilers it's already running at maximum speed
No, it isn't.
(only stuff like SSE3 and optimizing for the new larger caches actually allows for some more improvement)
If anything you said earlier had any merit, larger caches wouldn't help.
the P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!)
SSE2 isn't only for SIMD; it also provides a flat register model to circumvent the x87 stack.
for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want".
Too bad it doesn't work that way in the real world... SIMD isn't a general-purpose method of computing, it requires specially designed AND optimized code.
The P4s SIMD is already maxed out and running at full speed with most applications right now
Pure fallacy.
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps.
According to their roadmaps they were three months late.
AMD also kept moving their 90nm launch further and further back and are now the only one that still doesn't ship any 90nm-CPU (and no, the "revenue launch" of the Oakville now is a mere joke! It's just for the books, they don't actually ship anything!).
It means that they're selling processors to system builders.
So yes, the yields of the 90nm-P970 aren't as good as IBM hoped, but for a change it's no propaganda when Steve Jobs says "the whole industry has hit the wall" - he's completely right about that, which anybody can confirm that follows the industry...
Anyone who's been paying attention can tell you that the industry has not hit the wall.
Intel is starting to get their 90nm-problems fixed, but at what cost? The P4 is leaking so much current due to lack of SOI that it must be the first CPU on the planet that eats MORE power than its larger-scale predecessor at the same clock!
It's because of physics, not because they don't use SoI. SoI helps reduce leakage in some areas, but the tradeoff is higher wafer costs, and higher defect densities. Also consider the fact that Prescott has close to 3x as many transistors as Northwood.
So yes, AMD reached 2.4 GHz with 130nm and Intel 3.4 GHz with 130 nm. However, the P4-Design was built for high clockspeed and can't possibly be compared to an Execution-unit-loaded-CPU like the P970. The Opteron, while also featuring much less execttion units than the P970 is not that much different to an Athlon with SSE2, x86-64, a memory controller and larger cache.
The G5 doesn't have as much of a lead in execution resources as you think it does.
AMD reached 2.17 GHz in August 2002 with the Athlon 2600+. Now, exactly 2 years later, they're at 2.4 GHz. Sorry, but i really don't see any huge clock-scaling there!
They got to 2.4 GHz on 130 nm, while IBM is barely exceeding that with 90 nm. How hard is that to understand?
IBM just doesn't want to make a faster version of the 130nm P970 i assume.
It would just eat too much power for apple and IBM to tolerate, although it would technically probably be possible.
Die size is a huge motivating factor. IBM's priority is to make it smaller. That's why they didn't add any cache when they transitioned to 90nm. Smaller dies are less costly to produce, and they're using a very expensive fab process to make the PPC970.
The 130nm 3.4 GHz P4EE is a horrible kludge that Intel just threw together hastily BECAUSE Prescott was too late! They had no other choice to match the power of an integrated memory controller in the Athlon-FX because Prescott simply wasn't there!
They probably understimated AMD. I think the only reason that the P4EE exists at all was to counter the Athlon64, but it wasn't a hack; it was a core that had been in production for a long time, with a different market.
Dito the 2.4 GHz Opteron and Athlon-FX (can these actually be bought in volume anywhere? Like as in: Is there a system builder selling 200.000-350.000 of these per quarter, which is what apple puts through in P970s?), they're just makeshift because AMDs 90nm-CPUs are also delayed.
They're selling very well, based on the sales data. Also keep in mind the majority of Apple's sales recently have been laptops, and that they're still supply-limited on G5's.
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
Then maybe you should try applying your own standards, especially given how many execution resources Itanium has (and only a 7-stage pipeline, clearly not built for clock speed).
In case you haven't noticed: the 970FX is so far the only 90nm-CPU that eats LESS power than its 130nm-predecessor, like it's supposed to be...
That's not even accurate. AMD's 90nm design is lower power than their 130 nm design, and Intel has one also. P4 isn't Intel's only mainstream product, and I'm not talking about Celeron.
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube! ;)
Not always.
mattin
08-25-2004, 10:22 AM
Your arrogance is unbecoming, since you really don't know anything.
And this from a man who just claimed that FMAC-Instructions were just introduced to the PPC-ISA with the G5, that Alpha compiler knowhow is the bee's knees and that Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
I was characterizing manufacturing, not the processor architecture.
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The units are never all occupied.
Okay, so the FPU/SSE/MMX-Unit sits mostly idle waiting for instructions. Is that what you're trying to tell me, yes?
The problem is exactly the opposite, and the processor designers work hard to utilize idle resources.
And this is why SMT was such a huuuuge gain of 1x% (only under optimum circumstances ofcourse!) when implemented by Intel under the Hypnothreading-moniker, right? Did you actually notice that Intels Version of SMT quite often actually makes stuff SLOWER? Stuff like (oooh!) for example the SPEC-suite, which is supposed to be a broad representation of actual common code?
If you want to see SMT done right with a CPU that actually HAS the execution units to gain from it, go to the second company that implemented it and just kicked the living shit out of every other CPU including the stillborn Itanic.. Oops, that would be IBM i presume! ;-)
Let's better not even touch the huuuge problem of writing compilers that actually generate smooth code on braindead CPU-designs like the P4! ;-) You may ask the GCC-team how great this is!
The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time.
That doesn't help performance in the real world any,
Have you ever taken a look at the length of the altivec pipeline? Have you noticed that it's by far the longest in the CPU?
because it's very difficult to mix scalar and SIMD instructions to begin with.
If you code on the assembly level yes, but what if the compiler does it for you? IBM is improving their compiler pretty quickly. group formation is getting better and they're working on the auto-vectorizing part because VMX will soon play a VERY important role in IBMs plans. Remember my words...
Once Auto-vectorizing is in place mixing vector and scalar code should be well possible..
On top of that, altivec doesn't even support double precision anyway.
Where did i ever claim that it did? In fact i repeatedly said it didn't myself!
The fact remains that there are very very many cases where single precision floats are more than enough..
If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
Yes, and it can do double-precision arithmetic in SIMD, and has a dedicated load/store unit to keep it fed.
Oh, and the G5 has what? A box of Cheerios?
What exactly is the point of using SIMD when you only get 2 FP-ops per cycle max, when the G5 can do 4 in one cycle due to FMAC and 2 FPUs?
Altivec may be only single precision, but it sure as hell serves the term "SIMD" way way better than SSEx!...
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first? Did you know that the G4 and G5 can handle much much more open memory requests (16 i think!) at once?
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;-)
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual.
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Did you even ever hear of the term "out of order execution"?
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
If anything you said earlier had any merit, larger caches wouldn't help.
?? Please elaborate further.
The P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!)
SSE2 isn't only for SIMD; it also provides a flat register model to circumvent the x87 stack.
And Alitvec is not only for SIMD but also for prefetching data. And your point is?
for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want".
Too bad it doesn't work that way in the real world...
NASAs Craig Hunter chose Altivec for his Jet3D streaming simulation.
The Virginia Tech guys and many others are using the FPUs to compute -among other things- streaming models.
Apparently it DOES work that way in the real world!...
SIMD isn't a general-purpose method of computing, it requires specially designed AND optimized code.
Wrong. Auto-vectorization may by far not be as great as handwritten vector-code, but it certainly helped the P4 alot!
You do remember the time the P4 was introduced and there was NO SSE2-aware program around besides Quake3 and Windows Media Encoder? Which is why the P4 was beaten handily by both its 50% slower clocked predecessor and the Athlon in EVERYTHING except for these two programs? And did you noticed how this slowly changed when programs were compiled with the newer SSE2-aware intel-compilers (e.g. Cinema!)?
The P4s SIMD is already maxed out and running at full speed with most applications right now
Pure fallacy.
Excuse me, are you the same person that was praising the very high quality of Intels compilers a posting earlier?
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps.
According to their roadmaps they were three months late.
http://www.theregister.co.uk/2003/10/13/intel_tejas_delayed_until/
"The shift is a result of the 90nm Prescott being moved back from Q4 2003 to Q1 2004. Last August, Intel was saying 3.2GHz and 3.4GHz Prescotts would be shipping in volume in the current quarter [Q3/2003]."
http://www.theregister.co.uk/2003/07/10/prescott_to_clock_higher/
"The leaked roadmap, sent this time to Cnet,, pegs Prescott at 3.4GHz rather than 3.2GHz, ramping up to 3.6GHz during Q1 2004. [...] It will be launched in Q4.
The roadmap confirms previously reported October P4 price cuts, the first since the last round of reductions, last month. Those cuts will come on 26 October, suggesting Prescott will debut on or not long after that date."
http://www.theregister.co.uk/2003/04/08/qdi_springs_springdale_mobo/
"Published Tuesday 8th April 2003 08:25*GMT
The P4I865G will ship, says QDI, around the middle of this month, "at the same time Intel launches its new chipset". Intel is expected to launch Prescott, the CPU supporting the 800MHz FSB, at the same time."
http://www.theregister.co.uk/2003/08/08/intel_delays_dothan_debut/
"Roadmaps seen by PC Watch not so long ago had Dothan pegged for a September/October [2003] release."
But the best is this:
http://www.theregister.co.uk/2000/07/06/return_of_the_son/
"Published Thursday 6th July 2000 10:54*GMT
Intel's 479 pin son of Willamette, due for launch next year [2001!!], now has its very own codename, Prescott."
Anyway: It's nice of you to keep trying! ;-)
[Oakville 90nm AMD-Chip "Revenue Launch"]
It means that they're selling processors to system builders
It means that they're doing a paper launch for tax cuts in the current quarter. Notebooks with the chips can't be bought anywhere right now!
[90nm]
Anyone who's been paying attention can tell you that the industry has not hit the wall.
Rrright.. You are definately living in your own universe! ;-) I guess Intel released their 90nm-CPUs half a year late because they thought it was fun! And also AMD kept moving their 90nm-Release further and further back just because of the thrill. And TI planned 90nm for mid-2003 and shipped its first chip using it in January 2004 because they thought roadmaps were icky anyway.
http://www.electronicstalk.com/news/tex/tex213.html
http://www.microcontroller.com/news/ti_1ghz.asp
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm? Because they like a little company? Why do you think Intel canned half its Roadmap and moved the introduction of Dualcore from 2006 to 2005? And why is Dualcore all the rage all of a sudden? If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
It's because of physics, not because they don't use SoI.
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
Boy, that's some logic! ;-)
SoI helps reduce leakage in some areas, but the tradeoff is higher wafer costs, and higher defect densities.
Your point is moot. Yields are *always down when introducing ANYTHING new in the manufacturing process and also often in die design itself! Doesn't matter if it's a new technique or a die-shrink or a bigger cache (just ask Intel about "Pentium Pro"! >:-)
Also consider the fact that Prescott has close to 3x as many transistors as Northwood.
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
The G5 doesn't have as much of a lead in execution resources as you think it does.
Do i get proof for this? Or do you enjoy claiming stuff without proof?
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic: CPUs that can do 4 FP-ops per cycle max which is accounted for accordingly in the Top500 Rpeak.
Both the Opteron and the Xeon are in the lower class that can do only 2 FP-ops per cycle.
And yes, if you look at the actual yield the G5 is just a tiny bit below a Xeon using Kaizushige Gotos highly optimized dgemm. Xeon's problem is that with the G5 this means the P970 gets twice as much stuff done per cycle! ;-)
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
They got to 2.4 GHz on 130 nm, while IBM is barely exceeding that with 90 nm. How hard is that to understand?
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
SSDOI is not an easy beast to tame, that's for sure. But IBM rather faces the challenge instead of taking the easy way out making a 130 nm-CPU with 2.5 GHz that eats 110 Watts!
AMD did not "get" to 2.4 GHz at 130 nm (they'll get to 2.6 on 130nm by the end of the year btw!) - They HAD to do that, because the 90nm-process simply wasn't there yet!
IBM doesn't need to scale clock as badly as a company that makes a living of (mostly) selling CPUs only and which competes directly with Intel. Do you actually think IBM will ever introduce new CPUs every quarter like AMD and Intel do to keep their sharevalue happy? Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
They probably understimated AMD. I think the only reason that the P4EE exists at all was to counter the Athlon64, but it wasn't a hack; it was a core that had been in production for a long time, with a different market.
Gallatin isn't actually much of an own core. Just like Prestonia it's just a derivative of Northwood with VERY few changes.
But that just supports my point of view that the P4EE was just a kludge that was thrown together from ready parts! ;-)
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
[Quote] Then maybe you should try applying your own standards, especially given how many execution resources Itanium has (and only a 7-stage pipeline, clearly not built for clock speed).
I was deliberately applying YOUR standard, measuring by clock speed!
Point is: The G5 is the highest clocked CPU in the RISC- and EPIC-Camp. Plus it's ALSO loaded with execution units. The Virginia Tech guy had a reason for saying that Intels ironically got beaten on clockspeed when they decided on the G5 and against the Itanic!...
That's not even accurate. AMD's 90nm design is lower power than their 130 nm design, and Intel has one also. P4 isn't Intel's only mainstream product, and I'm not talking about Celeron.
In case you haven't noticed: The 90nm AMD Oakville is not actually shipping! As far as the Dothan is concerned: We all know what a "precise measure" Intels "Thermal Design Power" is. Dothans are specified for 21 Watts in 1.7 GHz thru 2 GHz. Since higher clock means more Watt it should be obvious that something is not quite right. The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it) shows that they're fighting with current leakage here, too!
This means that the Dothans will only draw less power as the Banias under maximum load.
Besides, mobile CPU seem hardly a proper example. Especially when they are a new core, like the Dothan, because new cores in mobile CPUs automatically mean that new power saving measures are incorporated, hence reduced power consumption are not necessarily due to die shrinks!
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube!
Not always.
Okay, so when did they not? Please do tell!
And this from a man who just claimed that FMAC-Instructions were just introduced to the PPC-ISA with the G5, that Alpha compiler knowhow is the bee's knees and that Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
I was characterizing manufacturing, not the processor architecture.
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The units are never all occupied.
Okay, so the FPU/SSE/MMX-Unit sits mostly idle waiting for instructions. Is that what you're trying to tell me, yes?
The problem is exactly the opposite, and the processor designers work hard to utilize idle resources.
And this is why SMT was such a huuuuge gain of 1x% (only under optimum circumstances ofcourse!) when implemented by Intel under the Hypnothreading-moniker, right? Did you actually notice that Intels Version of SMT quite often actually makes stuff SLOWER? Stuff like (oooh!) for example the SPEC-suite, which is supposed to be a broad representation of actual common code?
If you want to see SMT done right with a CPU that actually HAS the execution units to gain from it, go to the second company that implemented it and just kicked the living shit out of every other CPU including the stillborn Itanic.. Oops, that would be IBM i presume! ;-)
Let's better not even touch the huuuge problem of writing compilers that actually generate smooth code on braindead CPU-designs like the P4! ;-) You may ask the GCC-team how great this is!
The P970 (like the G4!) can execute both Altivec and FPU-commands at the same time.
That doesn't help performance in the real world any,
Have you ever taken a look at the length of the altivec pipeline? Have you noticed that it's by far the longest in the CPU?
because it's very difficult to mix scalar and SIMD instructions to begin with.
If you code on the assembly level yes, but what if the compiler does it for you? IBM is improving their compiler pretty quickly. group formation is getting better and they're working on the auto-vectorizing part because VMX will soon play a VERY important role in IBMs plans. Remember my words...
Once Auto-vectorizing is in place mixing vector and scalar code should be well possible..
On top of that, altivec doesn't even support double precision anyway.
Where did i ever claim that it did? In fact i repeatedly said it didn't myself!
The fact remains that there are very very many cases where single precision floats are more than enough..
If you actually took the time to "do your homework", like somebody said in the other thread, you'd have noticed that the bad P4-Design only has _one_ Execution Unit that does FPU-Commands, SSE1/2 and MMX.
Yes, and it can do double-precision arithmetic in SIMD, and has a dedicated load/store unit to keep it fed.
Oh, and the G5 has what? A box of Cheerios?
What exactly is the point of using SIMD when you only get 2 FP-ops per cycle max, when the G5 can do 4 in one cycle due to FMAC and 2 FPUs?
Altivec may be only single precision, but it sure as hell serves the term "SIMD" way way better than SSEx!...
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first? Did you know that the G4 and G5 can handle much much more open memory requests (16 i think!) at once?
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;-)
So theoretically a P970 can work on 2 FP-ops (technically 4 due to FMAC, but not in the same cycle!), 2 Integer-ops and 2 Altivec-ops (one permute, one VALU) in the same cycle, something that the P4 could never do (maximum is 2 Integer-ops and either two MMX-ops or SSE-ops or FP-ops!). Reality is not perfect ofcourse, but the compilers are getting better and better, and the potential can definately be seen!
No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual.
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Did you even ever hear of the term "out of order execution"?
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
If anything you said earlier had any merit, larger caches wouldn't help.
?? Please elaborate further.
The P970 is at the very beginning of what's actually possible. Auto-vectorization for example, which Intels compilers rely heavily upon (in fact the P4 couldn't hardly get anything done without it because its x87-FPU sucks really really bad!)
SSE2 isn't only for SIMD; it also provides a flat register model to circumvent the x87 stack.
And Alitvec is not only for SIMD but also for prefetching data. And your point is?
for example is so far not present in the P970. The point is that it's not even close to being as dependant on it as the P4 is, because it HAS 2 real proper DP-FPUs with FMAC to get Floating-point code done fast! It's not "either or" for the P970 but more "use whichever path you want".
Too bad it doesn't work that way in the real world...
NASAs Craig Hunter chose Altivec for his Jet3D streaming simulation.
The Virginia Tech guys and many others are using the FPUs to compute -among other things- streaming models.
Apparently it DOES work that way in the real world!...
SIMD isn't a general-purpose method of computing, it requires specially designed AND optimized code.
Wrong. Auto-vectorization may by far not be as great as handwritten vector-code, but it certainly helped the P4 alot!
You do remember the time the P4 was introduced and there was NO SSE2-aware program around besides Quake3 and Windows Media Encoder? Which is why the P4 was beaten handily by both its 50% slower clocked predecessor and the Athlon in EVERYTHING except for these two programs? And did you noticed how this slowly changed when programs were compiled with the newer SSE2-aware intel-compilers (e.g. Cinema!)?
The P4s SIMD is already maxed out and running at full speed with most applications right now
Pure fallacy.
Excuse me, are you the same person that was praising the very high quality of Intels compilers a posting earlier?
Now, let's get to the topic of manufacturing. Intel was more than half a year later with its 90nm-CPUs, which were supposed to be launching in mid-2003 according to their roadmaps.
According to their roadmaps they were three months late.
http://www.theregister.co.uk/2003/10/13/intel_tejas_delayed_until/
"The shift is a result of the 90nm Prescott being moved back from Q4 2003 to Q1 2004. Last August, Intel was saying 3.2GHz and 3.4GHz Prescotts would be shipping in volume in the current quarter [Q3/2003]."
http://www.theregister.co.uk/2003/07/10/prescott_to_clock_higher/
"The leaked roadmap, sent this time to Cnet,, pegs Prescott at 3.4GHz rather than 3.2GHz, ramping up to 3.6GHz during Q1 2004. [...] It will be launched in Q4.
The roadmap confirms previously reported October P4 price cuts, the first since the last round of reductions, last month. Those cuts will come on 26 October, suggesting Prescott will debut on or not long after that date."
http://www.theregister.co.uk/2003/04/08/qdi_springs_springdale_mobo/
"Published Tuesday 8th April 2003 08:25*GMT
The P4I865G will ship, says QDI, around the middle of this month, "at the same time Intel launches its new chipset". Intel is expected to launch Prescott, the CPU supporting the 800MHz FSB, at the same time."
http://www.theregister.co.uk/2003/08/08/intel_delays_dothan_debut/
"Roadmaps seen by PC Watch not so long ago had Dothan pegged for a September/October [2003] release."
But the best is this:
http://www.theregister.co.uk/2000/07/06/return_of_the_son/
"Published Thursday 6th July 2000 10:54*GMT
Intel's 479 pin son of Willamette, due for launch next year [2001!!], now has its very own codename, Prescott."
Anyway: It's nice of you to keep trying! ;-)
[Oakville 90nm AMD-Chip "Revenue Launch"]
It means that they're selling processors to system builders
It means that they're doing a paper launch for tax cuts in the current quarter. Notebooks with the chips can't be bought anywhere right now!
[90nm]
Anyone who's been paying attention can tell you that the industry has not hit the wall.
Rrright.. You are definately living in your own universe! ;-) I guess Intel released their 90nm-CPUs half a year late because they thought it was fun! And also AMD kept moving their 90nm-Release further and further back just because of the thrill. And TI planned 90nm for mid-2003 and shipped its first chip using it in January 2004 because they thought roadmaps were icky anyway.
http://www.electronicstalk.com/news/tex/tex213.html
http://www.microcontroller.com/news/ti_1ghz.asp
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm? Because they like a little company? Why do you think Intel canned half its Roadmap and moved the introduction of Dualcore from 2006 to 2005? And why is Dualcore all the rage all of a sudden? If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
It's because of physics, not because they don't use SoI.
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
Boy, that's some logic! ;-)
SoI helps reduce leakage in some areas, but the tradeoff is higher wafer costs, and higher defect densities.
Your point is moot. Yields are *always down when introducing ANYTHING new in the manufacturing process and also often in die design itself! Doesn't matter if it's a new technique or a die-shrink or a bigger cache (just ask Intel about "Pentium Pro"! >:-)
Also consider the fact that Prescott has close to 3x as many transistors as Northwood.
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
The G5 doesn't have as much of a lead in execution resources as you think it does.
Do i get proof for this? Or do you enjoy claiming stuff without proof?
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic: CPUs that can do 4 FP-ops per cycle max which is accounted for accordingly in the Top500 Rpeak.
Both the Opteron and the Xeon are in the lower class that can do only 2 FP-ops per cycle.
And yes, if you look at the actual yield the G5 is just a tiny bit below a Xeon using Kaizushige Gotos highly optimized dgemm. Xeon's problem is that with the G5 this means the P970 gets twice as much stuff done per cycle! ;-)
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
They got to 2.4 GHz on 130 nm, while IBM is barely exceeding that with 90 nm. How hard is that to understand?
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
SSDOI is not an easy beast to tame, that's for sure. But IBM rather faces the challenge instead of taking the easy way out making a 130 nm-CPU with 2.5 GHz that eats 110 Watts!
AMD did not "get" to 2.4 GHz at 130 nm (they'll get to 2.6 on 130nm by the end of the year btw!) - They HAD to do that, because the 90nm-process simply wasn't there yet!
IBM doesn't need to scale clock as badly as a company that makes a living of (mostly) selling CPUs only and which competes directly with Intel. Do you actually think IBM will ever introduce new CPUs every quarter like AMD and Intel do to keep their sharevalue happy? Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
They probably understimated AMD. I think the only reason that the P4EE exists at all was to counter the Athlon64, but it wasn't a hack; it was a core that had been in production for a long time, with a different market.
Gallatin isn't actually much of an own core. Just like Prestonia it's just a derivative of Northwood with VERY few changes.
But that just supports my point of view that the P4EE was just a kludge that was thrown together from ready parts! ;-)
The real basis for comparison is not x86-CPUs but other RISC-CPUs. The P970 is by far the fastest clocked one among all of them, even IBMs own Power series! Granted, there ain't many left thanks to the %&&$ Itanic, but all the ones left over including the Itanic only come in a much lower clock!
[Quote] Then maybe you should try applying your own standards, especially given how many execution resources Itanium has (and only a 7-stage pipeline, clearly not built for clock speed).
I was deliberately applying YOUR standard, measuring by clock speed!
Point is: The G5 is the highest clocked CPU in the RISC- and EPIC-Camp. Plus it's ALSO loaded with execution units. The Virginia Tech guy had a reason for saying that Intels ironically got beaten on clockspeed when they decided on the G5 and against the Itanic!...
That's not even accurate. AMD's 90nm design is lower power than their 130 nm design, and Intel has one also. P4 isn't Intel's only mainstream product, and I'm not talking about Celeron.
In case you haven't noticed: The 90nm AMD Oakville is not actually shipping! As far as the Dothan is concerned: We all know what a "precise measure" Intels "Thermal Design Power" is. Dothans are specified for 21 Watts in 1.7 GHz thru 2 GHz. Since higher clock means more Watt it should be obvious that something is not quite right. The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it) shows that they're fighting with current leakage here, too!
This means that the Dothans will only draw less power as the Banias under maximum load.
Besides, mobile CPU seem hardly a proper example. Especially when they are a new core, like the Dothan, because new cores in mobile CPUs automatically mean that new power saving measures are incorporated, hence reduced power consumption are not necessarily due to die shrinks!
Oh, and btw: Motorola has always shipped more CPUs than IBM. This is probably due to the fact that Motorola predominantly makes embedded CPUs that go into very many appliances and IBM has only entered the mainstream market in the last year with the P970 and Gecko for the Gamecube!
Not always.
Okay, so when did they not? Please do tell!
Thalaxis
08-25-2004, 04:38 PM
And this from a man who just claimed that FMAC-Instructions were just introduced to the PPC-ISA with the G5
I didn't say anything like that at all.
Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
That's also entirely your fabrication.
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The purpose in long pipelines is to raise clock speed. If you have a long pipeline, you should be able to reach a high clock speed, no matter how wide your processor is.
And this is why SMT was such a huuuuge gain of 1x% (only under optimum circumstances ofcourse!)
The 20% gain I've been getting with Cinema has been quite nice.
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first?
You actually mentioned pre-fetch, but apparently you don't understand what that means.
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;-)
Or in IBM's new Xeon system, 64.
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Yet another fabrication on your part.
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
Do you know what "issue" means?
It means that they're doing a paper launch for tax cuts in the current quarter. Notebooks with the chips can't be bought anywhere right now!
Did it occur to you that it might take more than a week to ship the processors, build the latptops, test them, package, them, and then release them to distribution? Is your mind really so small that you can't handle that simple issue?
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm?
Obviously, it's because, unlike Intel, they can't afford to do it on their own.
They've also said as much publicly.
If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
Intel's had dual and multi core processors on their roadmap for quite a while. I never said that clock speeds weren't capping out, I said that the industry wasn't.
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
Actually, if you tried actually thinking you might have figured this one out... Intel's problem was heat. From a business point of view, Prescott has been very successful, in that it's been generating a lot of revenue. That indicates success on the production side.
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
You took "it doesn't fix everything" to mean that it does nothing?
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
Cache does suffer from leakage. Being cache doesn't make it immune to physics. It's just harder to prevent leakage in logic than in SRAMs.
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic:
No, it doesn't. At least, not in the real world.
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
Because it was cheap, according to them. At least, it was cheaper than their first choice.
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
You ought to read my reply to that again. I gave you another reason that they wanted to move to 90 nm as soon as possible.
Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
Of course not. They wouldn't be able to stay in the race anyway, and they know it. They already ceded victory to Intel in any case, when they launched their POWER Everywhere program, and said that they were therefore going to focus on markets Intel wasn't involved in.
I was deliberately applying YOUR standard, measuring by clock speed!
Yet another one of your assinine fabrications. If all you're going to do is put words in my mouth, you're only going to prove ever more decisively that you're a dolt.
As far as the Dothan is concerned: We all know what a "precise measure" Intels "Thermal Design Power" is.
It's more precise than anything IBM is willing to divulge.
The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it)
IBM and AMD also didn't double an already large L2, either.
I didn't say anything like that at all.
Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
That's also entirely your fabrication.
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The purpose in long pipelines is to raise clock speed. If you have a long pipeline, you should be able to reach a high clock speed, no matter how wide your processor is.
And this is why SMT was such a huuuuge gain of 1x% (only under optimum circumstances ofcourse!)
The 20% gain I've been getting with Cinema has been quite nice.
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first?
You actually mentioned pre-fetch, but apparently you don't understand what that means.
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;-)
Or in IBM's new Xeon system, 64.
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Yet another fabrication on your part.
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
Do you know what "issue" means?
It means that they're doing a paper launch for tax cuts in the current quarter. Notebooks with the chips can't be bought anywhere right now!
Did it occur to you that it might take more than a week to ship the processors, build the latptops, test them, package, them, and then release them to distribution? Is your mind really so small that you can't handle that simple issue?
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm?
Obviously, it's because, unlike Intel, they can't afford to do it on their own.
They've also said as much publicly.
If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
Intel's had dual and multi core processors on their roadmap for quite a while. I never said that clock speeds weren't capping out, I said that the industry wasn't.
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
Actually, if you tried actually thinking you might have figured this one out... Intel's problem was heat. From a business point of view, Prescott has been very successful, in that it's been generating a lot of revenue. That indicates success on the production side.
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
You took "it doesn't fix everything" to mean that it does nothing?
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
Cache does suffer from leakage. Being cache doesn't make it immune to physics. It's just harder to prevent leakage in logic than in SRAMs.
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic:
No, it doesn't. At least, not in the real world.
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
Because it was cheap, according to them. At least, it was cheaper than their first choice.
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
You ought to read my reply to that again. I gave you another reason that they wanted to move to 90 nm as soon as possible.
Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
Of course not. They wouldn't be able to stay in the race anyway, and they know it. They already ceded victory to Intel in any case, when they launched their POWER Everywhere program, and said that they were therefore going to focus on markets Intel wasn't involved in.
I was deliberately applying YOUR standard, measuring by clock speed!
Yet another one of your assinine fabrications. If all you're going to do is put words in my mouth, you're only going to prove ever more decisively that you're a dolt.
As far as the Dothan is concerned: We all know what a "precise measure" Intels "Thermal Design Power" is.
It's more precise than anything IBM is willing to divulge.
The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it)
IBM and AMD also didn't double an already large L2, either.
mattin
08-25-2004, 08:26 PM
And this from a man who just claimed that FMAC-Instructions were just introduced to the PPC-ISA with the G5
I didn't say anything like that at all.http://www.cgtalk.com/showpost.php?p=1516691&postcount=72
"I've read the tech data. It's creative marketing; the G4 has two add/mul/load units, and the G5 has two add/mul/load units. The difference is that the G5 has FMA instructions, which can double throughput... but apparently either Apple's marketeers don't know what that means, or they think that their customer base isn't smart enough to grasp the difference.
Then again, it wouldn't be the first time Apple lied blatantly to the public."
Tough luck i guess! ;) Hint: Actually remembering what you said yourself saves from embarrassments like this!
Fact: Every Motorola-CPU back to the G3 or earlier has FMAC. As do IBMs POWER-CPUs. Your claim was completely false, face it!
As was your claim that the G4 has 2 FPUs, but that's been proven to you ad infinum, yet you're still in denial in spite of overwhelming evidence - ofcourse without backing ANY of _your_ claims up with facts and links, but this is standard behaviour for you!
Didn't i see a disclaimer on here that people posting on here are supposed to back up their claims with links? I have yet to see one single posting from you where you actually follow this common practice!
Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
That's also entirely your fabrication.http://www.cgtalk.com/showpost.php?p=1515546&postcount=42
[Posted in a thread about Optimizations in C4D, which *only* runs on x86 and PPC!]
"Apple's compiler suite is based on GCC, which is notorious for mediocre performance, especially with newer architectures. And Intel on the other hand has one of the best compiler development teams in the world, especially now that they brought pretty much the entire Alpha compiler team on board."
So you'll probably be trying to tell us you're suddenly talking about SAP running on the Itanic and not C4D. Yeah, nice try! ;)
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The purpose in long pipelines is to raise clock speed. If you have a long pipeline, you should be able to reach a high clock speed, no matter how wide your processor is.Again: How does pipeline length affect manufacturing?
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first?
You actually mentioned pre-fetch, but apparently you don't understand what that means.
I *am* talking about prefetches, brainiac!
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;)
Or in IBM's new Xeon system, 64.in 32 pairs of 2 CPUs, all interconnected with a crossbar and using dedicated chipsets to manage the pairs, just like with serverworks, thanks very much! ;) Have fun while cache snooping in this! Face it: Xeons with more than 2 CPUs are like lots of Dual-Blades in a smaller space and with maybe less latency, nothing more!... You know, the Duals-in-a-rack that ISPs and many others obviously enjoy so much buying! ;)
P4-Xeons must be the worst scaling CPUs on the planet... Right now since the G5 was released they're the only one left that still uses a SHARED FSB! Given the age of the Athlons EV6-bus this is truly embarassing, even more embarrassing in light of the K8's embedded memory controller (Kudos to AMD for that! The industry is obviously honoring that!)
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Yet another fabrication on your part.
http://cgtalk.com/showpost.php?p=1521951&postcount=26
I said: "So theoretically a P970 can work on 2 FP-ops 2 Integer-ops and 2 Altivec-ops in the same cycle"
You said: "No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual."
I said "work on in the same cycle", you said "issue per clock cycle". I don't know, but to me it sounds like these two VERY different things are actually the same to you. Which means that you obviously don't even have a clue how Out-of-order-execution actually works!... And this is just embarrassing for a guy that claims to be in the know about CPU-tech! ;)
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
Do you know what "issue" means?Yes. But I have a striking fear that you do NOT! <:-)
<SIMD and SSE2 as well as proof of Intel's 90nm-problems snipped by you - Can we consider the topic settled?>
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm?
Obviously, it's because, unlike Intel, they can't afford to do it on their own.
They've also said as much publicly.Good boy! Next question: What does it mean when they're joining forces NOW, just when the 90nm-introductions where ALL horribly late and didn't go smooth at all (contrary to previous die-shrinks!)?
Don't worry, we're getting you there eventually! ;)
If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
Intel's had dual and multi core processors on their roadmap for quite a while.Well - duh! Why did you snip out the part of the sentence where i said "Why do you think Intel canned half its Roadmap and moved the introduction of Dualcore from 2006 to 2005?" - Have we already reached the point where you're trying to claim the other party said something wrong by leaving out certain parts of their posting, yes?
I didn't say anything like that at all.http://www.cgtalk.com/showpost.php?p=1516691&postcount=72
"I've read the tech data. It's creative marketing; the G4 has two add/mul/load units, and the G5 has two add/mul/load units. The difference is that the G5 has FMA instructions, which can double throughput... but apparently either Apple's marketeers don't know what that means, or they think that their customer base isn't smart enough to grasp the difference.
Then again, it wouldn't be the first time Apple lied blatantly to the public."
Tough luck i guess! ;) Hint: Actually remembering what you said yourself saves from embarrassments like this!
Fact: Every Motorola-CPU back to the G3 or earlier has FMAC. As do IBMs POWER-CPUs. Your claim was completely false, face it!
As was your claim that the G4 has 2 FPUs, but that's been proven to you ad infinum, yet you're still in denial in spite of overwhelming evidence - ofcourse without backing ANY of _your_ claims up with facts and links, but this is standard behaviour for you!
Didn't i see a disclaimer on here that people posting on here are supposed to back up their claims with links? I have yet to see one single posting from you where you actually follow this common practice!
Alpha-people are working on x86-CPUs at Intel. Fascinating stuff.
That's also entirely your fabrication.http://www.cgtalk.com/showpost.php?p=1515546&postcount=42
[Posted in a thread about Optimizations in C4D, which *only* runs on x86 and PPC!]
"Apple's compiler suite is based on GCC, which is notorious for mediocre performance, especially with newer architectures. And Intel on the other hand has one of the best compiler development teams in the world, especially now that they brought pretty much the entire Alpha compiler team on board."
So you'll probably be trying to tell us you're suddenly talking about SAP running on the Itanic and not C4D. Yeah, nice try! ;)
BS. If you talk about pipeline stages you are not talking about manufacturing but about CPU architecture. Pipeline stages have nothing to do *at all* with current leakage or other manufacturing related topics.
The purpose in long pipelines is to raise clock speed. If you have a long pipeline, you should be able to reach a high clock speed, no matter how wide your processor is.Again: How does pipeline length affect manufacturing?
Oh, and btw: Since you're so fond of LSUs: Did you actually know that the braindead P4-design can only handle 2 open memory transfers at the same time, if a third needs to be issued the CPU has to sit idle waiting for the data to arrive first?
You actually mentioned pre-fetch, but apparently you don't understand what that means.
I *am* talking about prefetches, brainiac!
Yes, kids, there's a reason why Xeons only come in pairs (or that kludge of Xeon-MP-pairs Serverworks calls a "multi-node-design"! >;)
Or in IBM's new Xeon system, 64.in 32 pairs of 2 CPUs, all interconnected with a crossbar and using dedicated chipsets to manage the pairs, just like with serverworks, thanks very much! ;) Have fun while cache snooping in this! Face it: Xeons with more than 2 CPUs are like lots of Dual-Blades in a smaller space and with maybe less latency, nothing more!... You know, the Duals-in-a-rack that ISPs and many others obviously enjoy so much buying! ;)
P4-Xeons must be the worst scaling CPUs on the planet... Right now since the G5 was released they're the only one left that still uses a SHARED FSB! Given the age of the Athlons EV6-bus this is truly embarassing, even more embarrassing in light of the K8's embedded memory controller (Kudos to AMD for that! The industry is obviously honoring that!)
Oh, so you're saying that all instructions all units in a CPU are working on in one cycle were issued in the same cycle? Boy, your understanding of CPU architecture is even worse than i thought...
Yet another fabrication on your part.
http://cgtalk.com/showpost.php?p=1521951&postcount=26
I said: "So theoretically a P970 can work on 2 FP-ops 2 Integer-ops and 2 Altivec-ops in the same cycle"
You said: "No, it can't. It can't ever issue more than 5 instructions per clock cycle, and one has to be a branch. You're wrong again... as usual."
I said "work on in the same cycle", you said "issue per clock cycle". I don't know, but to me it sounds like these two VERY different things are actually the same to you. Which means that you obviously don't even have a clue how Out-of-order-execution actually works!... And this is just embarrassing for a guy that claims to be in the know about CPU-tech! ;)
I don't know how you turned my "work on" to "issue", thinking you'd get away with it, but i guess that's the ways of your twisted mind..
Do you know what "issue" means?Yes. But I have a striking fear that you do NOT! <:-)
<SIMD and SSE2 as well as proof of Intel's 90nm-problems snipped by you - Can we consider the topic settled?>
Hello, why do you think IBM, AMD, Samsung, Chartered SemiCon, Sony, Toshiba and Infineon are all joining forces to develop 65nm?
Obviously, it's because, unlike Intel, they can't afford to do it on their own.
They've also said as much publicly.Good boy! Next question: What does it mean when they're joining forces NOW, just when the 90nm-introductions where ALL horribly late and didn't go smooth at all (contrary to previous die-shrinks!)?
Don't worry, we're getting you there eventually! ;)
If MHz kept scaling like expected, it shouldn't be necessary to make Dualcore-CPUs, which yield no gain whatsoever with any games except for Quake3 and almost never any with regular consumer-apps!
Intel's had dual and multi core processors on their roadmap for quite a while.Well - duh! Why did you snip out the part of the sentence where i said "Why do you think Intel canned half its Roadmap and moved the introduction of Dualcore from 2006 to 2005?" - Have we already reached the point where you're trying to claim the other party said something wrong by leaving out certain parts of their posting, yes?
mattin
08-25-2004, 08:27 PM
I never said that clock speeds weren't capping out, I said that the industry wasn't.What leads you to believe Steve was claiming that the progress in Computer development in general (="the industry") has now completely stopped? Why on earth should he claim such a stupid thing? It depends on what Steve actually meant by "hit the wall". Since claiming there won't be *any* more scaling ("capping out") would be pretty ridiculous (who'd ever believe or claim *that* in the computer industry?) i guess he meant "hit an unexpected obstacle", which is 100% true, since ALL 90nm-Introductions were delayed and riddled with initial manufacturing problems and yields! Did you hear that Intel-buddy Dell threw out the Prescott a few weeks after its release in February cause Intel just couldn't deliver enough CPUs for an own product line? (yes, i know, they're back by now!)
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
Actually, if you tried actually thinking you might have figured this one out... Intel's problem was heat.Intels problem wasn't current leakage but heat. Ooookay! <:-) I guess now you've just destroyed the last bit of credibility you had...
http://www.infoworld.com/article/04/07/19/HNibmchipgroup_1.html
"Power leakage has been a primary concern in the 90-nanometer transition. Transistors are getting so small that electrical current can leak out of the transistors as heat, which creates problems for system designers. In previous process technology transitions, chip makers have been able to reduce power consumption, but many 90-nanometer chips consume just as much power as their predecessors. Intel's Prescott chip actually consumes more power than its older counterpart at similar clock speeds."
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
You took "it doesn't fix everything" to mean that it does nothing?[/i]You said " It's because of physics, not because they don't use SoI." SOI is a process solely designed to counter certain physical effects, which means your sentence is redundant and complete BS. You know the famous bushism "it's not the pollution that's killing our environment, it's the impurities in our air and water"? Well, that's pretty much exactly what you said just now! ;)
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
Cache does suffer from leakage. Being cache doesn't make it immune to physics. It's just harder to prevent leakage in logic than in SRAMs.Please do provide proof for this statement! Just ONCE, pretty please!...
Explain to me how Intel (or any other manufacturer!) would optimize hotspots in SRAM-cells when their content can be ANY possible combination of bits! ;)
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic:
No, it doesn't. At least, not in the real world.Can you actually do more than just contradict? I provided reasoning for my point of view. Where is yours? I probably will never see it...
In the realworld a G5-cluster was a wee bit ahead of a Xeon-cluster with 300 more CPUs clocked 50% faster. It also kicked the ass of an Itanic-cluster with 25% less clock and 240 CPUs less - by a healthy 20% margin!
Furthermore it also kicked the ass of an Opteron-Cluster with 616 CPUs more at the same clock - by 28%!
<cleese>
I came here for an argument! An argument is not just gainsaying of anything the other person says!
</cleese>
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
Because it was cheap, according to them. At least, it was cheaper than their first choice.Well, why don't they build a cluster from Celerons then? These are even WAY WAY cheaper! ;)
I guess the reason was more "cheap AND powerful", but i guess hell would rather freeze over before you admitted that! ;) Even in spite of the overwhelming evidence (see above!)
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
You ought to read my reply to that again. I gave you another reason that they wanted to move to 90 nm as soon as possible.
Which would be? I just can't seem to find it!...
Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
Of course not. They wouldn't be able to stay in the race anyway, and they know it.Hm, looking at the humiliating Power5-vs-Itanic figures I'd say they kicked some _very serious_ Intel-butt! ;)
How long will it take Intel to get a Dual-Core-CPU out, which IBM has been selling for years? Who pioneered Copper, MCM, FCBGA, low-k dielectrica, SOI and a whole bunch of other manufacturing techniques? Hint: It wasn't Intel! ;)
They already ceded victory to Intel in any case, when they launched their POWER Everywhere program, and said that they were therefore going to focus on markets Intel wasn't involved in.
Like - Xbox consoles, yes? ;)
All 3 next-gen consoles will be PPC-based, which will generate a HUGE toolchain and coding/optimizing-knowhow (which will be very good for the mac!). Intel itself even wants to see x86 dead, but those b'stards at AMD just won't let it kill x86! IBM is licensing their cores and fabs to interested people. Intel just killed 3 CPUs on their roadmap and just introduced a new CPU with features it tells developers to better not use (EMT64). The whole PC-camp is caught between x86-64, x86 and IA64 and NOBODY can seriously project what the outcome will be! Meanwhile in the PPC camp the 64bit-transition is going as smoothly as possibly imaginable and IBM is pretty much set to profit greatly from the confusion in the PC-camp!
I was deliberately applying YOUR standard, measuring by clock speed!
Yet another one of your assinine fabrications. If all you're going to do is put words in my mouth, you're only going to prove ever more decisively that you're a dolt.Did you or did you not compare how much MHz the different manufacturers reached with an X-stage pipeline, judging their "performance" from that?
btw: "dolt", "fool" etc - It's nice to see people turning to insults first, it always tells me my job of pointing out false claims and contradictions was well done! ;)
The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it)
IBM and AMD also didn't double an already large L2, either.http://www.hothardware.com/viewarticle.cfm?articleid=260&catid=1
"Not to mention the fact that an additional 256K (total of 512K) of on die cache has been added to the Pentium 4, to improve latency.*[...] The all new Northwood Pentium 4 core now runs at a significantly lower power 1.5V core voltage. [...]*The smaller the die, the less power it consumes in addition to the inherently higher clock speeds that are able to be produced.* Yields for this new P4 core have reached new heights in clock speed, now at 2.2GHz. for the top end processor.* From a power consumption perspective, a 2GHz. "Willy" consumes about 72 watts of power.* The new Northwood core at 2.2GHz. consumes 55 watts."
As always, you fail to research your claims and your flight is grounded by hard facts! ;)
It doesn't matter which company making 90nm-CPUs you're looking at: Intel, AMD, IBM, Texas Instruments, Sony (their supposed 90nm-PS2-Chip was a lie!) - they all had delays in 90nm and major problems with current leakage! You must be the only person on the planet not realizing this...
Actually, if you tried actually thinking you might have figured this one out... Intel's problem was heat.Intels problem wasn't current leakage but heat. Ooookay! <:-) I guess now you've just destroyed the last bit of credibility you had...
http://www.infoworld.com/article/04/07/19/HNibmchipgroup_1.html
"Power leakage has been a primary concern in the 90-nanometer transition. Transistors are getting so small that electrical current can leak out of the transistors as heat, which creates problems for system designers. In previous process technology transitions, chip makers have been able to reduce power consumption, but many 90-nanometer chips consume just as much power as their predecessors. Intel's Prescott chip actually consumes more power than its older counterpart at similar clock speeds."
Mmmmkkay... So SOI is not a process that is intended to counter physical effects like unwanted shorts in the silicon?
You took "it doesn't fix everything" to mean that it does nothing?[/i]You said " It's because of physics, not because they don't use SoI." SOI is a process solely designed to counter certain physical effects, which means your sentence is redundant and complete BS. You know the famous bushism "it's not the pollution that's killing our environment, it's the impurities in our air and water"? Well, that's pretty much exactly what you said just now! ;)
Most of which are SRAM-cells for the Cache. Which don't suffer from current leakage, because Cache doesn't have hotspots like the actual CPU-logic does!
Cache does suffer from leakage. Being cache doesn't make it immune to physics. It's just harder to prevent leakage in logic than in SRAMs.Please do provide proof for this statement! Just ONCE, pretty please!...
Explain to me how Intel (or any other manufacturer!) would optimize hotspots in SRAM-cells when their content can be ANY possible combination of bits! ;)
Fact: The G5 plays in the same "king" class of CPUs as the Power3, Power4 and Itanic:
No, it doesn't. At least, not in the real world.Can you actually do more than just contradict? I provided reasoning for my point of view. Where is yours? I probably will never see it...
In the realworld a G5-cluster was a wee bit ahead of a Xeon-cluster with 300 more CPUs clocked 50% faster. It also kicked the ass of an Itanic-cluster with 25% less clock and 240 CPUs less - by a healthy 20% margin!
Furthermore it also kicked the ass of an Opteron-Cluster with 616 CPUs more at the same clock - by 28%!
<cleese>
I came here for an argument! An argument is not just gainsaying of anything the other person says!
</cleese>
Why do you think Virginia Tech chose exactly the G5 for their homebrew-cluster?
Because it was cheap, according to them. At least, it was cheaper than their first choice.Well, why don't they build a cluster from Celerons then? These are even WAY WAY cheaper! ;)
I guess the reason was more "cheap AND powerful", but i guess hell would rather freeze over before you admitted that! ;) Even in spite of the overwhelming evidence (see above!)
And how hard is it to understand that IBM most likely never WANTED to make a faster 130nm-CPU and prefers to get their 90nm fixed?
You ought to read my reply to that again. I gave you another reason that they wanted to move to 90 nm as soon as possible.
Which would be? I just can't seem to find it!...
Will just not happen, no matter how good the manufacturing, because IBM just doesn't sell single CPUs to the end-user!...
Of course not. They wouldn't be able to stay in the race anyway, and they know it.Hm, looking at the humiliating Power5-vs-Itanic figures I'd say they kicked some _very serious_ Intel-butt! ;)
How long will it take Intel to get a Dual-Core-CPU out, which IBM has been selling for years? Who pioneered Copper, MCM, FCBGA, low-k dielectrica, SOI and a whole bunch of other manufacturing techniques? Hint: It wasn't Intel! ;)
They already ceded victory to Intel in any case, when they launched their POWER Everywhere program, and said that they were therefore going to focus on markets Intel wasn't involved in.
Like - Xbox consoles, yes? ;)
All 3 next-gen consoles will be PPC-based, which will generate a HUGE toolchain and coding/optimizing-knowhow (which will be very good for the mac!). Intel itself even wants to see x86 dead, but those b'stards at AMD just won't let it kill x86! IBM is licensing their cores and fabs to interested people. Intel just killed 3 CPUs on their roadmap and just introduced a new CPU with features it tells developers to better not use (EMT64). The whole PC-camp is caught between x86-64, x86 and IA64 and NOBODY can seriously project what the outcome will be! Meanwhile in the PPC camp the 64bit-transition is going as smoothly as possibly imaginable and IBM is pretty much set to profit greatly from the confusion in the PC-camp!
I was deliberately applying YOUR standard, measuring by clock speed!
Yet another one of your assinine fabrications. If all you're going to do is put words in my mouth, you're only going to prove ever more decisively that you're a dolt.Did you or did you not compare how much MHz the different manufacturers reached with an X-stage pipeline, judging their "performance" from that?
btw: "dolt", "fool" etc - It's nice to see people turning to insults first, it always tells me my job of pointing out false claims and contradictions was well done! ;)
The fact that Intel couldn't lower the voltage in the Dothans as it is custom with a die shrink (IBM did it, AMD did it)
IBM and AMD also didn't double an already large L2, either.http://www.hothardware.com/viewarticle.cfm?articleid=260&catid=1
"Not to mention the fact that an additional 256K (total of 512K) of on die cache has been added to the Pentium 4, to improve latency.*[...] The all new Northwood Pentium 4 core now runs at a significantly lower power 1.5V core voltage. [...]*The smaller the die, the less power it consumes in addition to the inherently higher clock speeds that are able to be produced.* Yields for this new P4 core have reached new heights in clock speed, now at 2.2GHz. for the top end processor.* From a power consumption perspective, a 2GHz. "Willy" consumes about 72 watts of power.* The new Northwood core at 2.2GHz. consumes 55 watts."
As always, you fail to research your claims and your flight is grounded by hard facts! ;)
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